# Rtl P4 Implement

> Phase 4 full RTL implementation from uarch specs with lint, review, and unit tests. Use when user says 'implement RTL', 'write RTL', or 'Phase 4'.

- Skill: `babyworm/rtl-p4-implement` (Agent Skill)
- Install (CLI): `npx skillmds@latest add babyworm/rtl-p4-implement`
- Raw SKILL.md: https://api.skillmd.com/api/skills/babyworm/rtl-p4-implement/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: babyworm (https://skillmd.com/u/babyworm)
- Updated: 2026-09-17
- Page: https://skillmd.com/skills/babyworm/rtl-p4-implement

---


<Purpose>
Execute Phase 4 RTL implementation pipeline. Implements SystemVerilog modules from
μArch specs through a 10-Wave pipeline: Write → Lint → Fix → Review → Bugfix →
UnitTest → CDC → Protocol → Refactor → IntegrationGate.
</Purpose>

<Use_When>
- Phase 3 μArch specs are complete and RTL coding is needed
- User says "implement RTL", "write RTL", "Phase 4", "code modules"
- Need lint-clean, unit-tested SystemVerilog modules
- Need the full 10-Wave implementation pipeline with comprehensive review/fix/refactor
- Need richer Phase-4 artifacts before handoff to Phase 5
</Use_When>

<Do_Not_Use_When>
- Phase 3 μArch specs are not complete (run rtl-p3-uarch-design first)
- Only need a single module bug fix (use rtl-p4s-bugfix)
- Need RTL + verification together from uarch (use rat-p4p5-impl-verify)
- Need a faster minimal Phase-4 sanity loop first (use rtl-p4-rapid-impl)
</Do_Not_Use_When>

## Prerequisites

Phase 3 completion required:
- At least one μArch spec in `docs/phase-3-uarch/` must exist

If prerequisite is missing: WARNING — recommend running `/rtl-agent-team:rtl-p3-uarch-design`.
Proceed with available artifacts — orchestrator will adapt scope.

## Execution

Task(subagent_type="rtl-agent-team:p4-implement-orchestrator",
     prompt="Execute Phase 4 RTL implementation. User input: $ARGUMENTS")

Do not perform any work directly.
The orchestrator agent manages module enumeration, 10-Wave sequencing,
parallel task dispatch, and phase gate verification.

## Compliance Notes

- After each implementation wave completes (lint + unit test), invoke compliance-checker against P1+P2+P3 iron requirements
- RTL implementation must comply with all upstream iron requirements
- Per-wave compliance ensures regressions are caught before the integration gate (W10)
- Wave 0 includes test plan generation (Step 0b) — test scenarios are derived from
  uarch spec before RTL implementation begins, following TDD principles.

## Output

- `rtl/*/*.sv` — lint-clean SystemVerilog modules
- `sim/*/tb_*.sv` — per-module unit test testbenches
- `docs/phase-4-rtl/` — Stream B design documents and implementation summary
- `reviews/phase-4-rtl/` — lint reports, code review reports, and wave completion records