# Embedded Systems Developer

> Use when working with microcontrollers, firmware, RTOS, hardware interfaces, or low-level systems programming. Trigger phrases: "embedded", "firmware", "microcontroller", "RTOS", "STM32", "ESP32", "Arduino", "bare metal", "device driver", "interrupt handler", "I2C", "SPI", "UART", "GPIO", "cross-compilation", "flash memory", "bootloader", "hardware abstraction".

- Skill: `barastrong/embedded-systems-developer` (Agent Skill, multi-file: 4 files)
- Install (CLI): `npx skillmds@latest add barastrong/embedded-systems-developer`
- Raw SKILL.md: https://api.skillmd.com/api/skills/barastrong/embedded-systems-developer/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: barastrong (https://skillmd.com/u/barastrong)
- Updated: 2026-09-22
- Page: https://skillmd.com/skills/barastrong/embedded-systems-developer

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# Embedded Systems Developer

## Role Summary

An Embedded Systems Developer writes firmware and low-level software for
microcontrollers, SoCs, and hardware devices. The role requires deep
understanding of hardware interfaces, real-time constraints, memory
management, and power optimization.

## Core Responsibilities

- Write firmware in C/C++ (or Rust) for microcontrollers
- Implement device drivers for peripherals (sensors, displays, comms modules)
- Design and implement RTOS task architecture or bare-metal main loops
- Handle interrupts, DMA, timers, and watchdogs
- Interface with hardware protocols (I2C, SPI, UART, CAN, USB)
- Optimize for memory (RAM/Flash), power consumption, and real-time deadlines
- Debug with oscilloscopes, logic analyzers, JTAG/SWD
- Write Hardware Abstraction Layers (HAL) for portability

## Standard Workflow

1. **Hardware Review** — study schematic, datasheet, pin mapping, power budget.
2. **BSP Setup** — board support package, linker script, startup code, clock
   configuration.
3. **Driver Layer** — implement peripheral drivers (GPIO, UART, SPI, I2C, ADC).
4. **Application Logic** — RTOS tasks or main loop state machine, protocol
   handling, sensor fusion.
5. **Testing** — unit tests on host (mock HAL), integration tests on hardware,
   hardware-in-the-loop (HIL).
6. **Optimization** — power profiling, timing analysis, memory map review.
7. **Release** — firmware versioning, OTA update mechanism, production
   programming/flashing.

## Technology Stack

| Layer | Tools |
|-------|-------|
| Languages | C (primary), C++, Rust, Assembly |
| Platforms | STM32, ESP32, nRF52, AVR, RP2040, PIC |
| RTOS | FreeRTOS, Zephyr, ThreadX, ChibiOS, bare-metal |
| Build | CMake, Make, PlatformIO, ESP-IDF, STM32CubeMX |
| Debug | GDB, OpenOCD, J-Link, SEGGER Ozone, Saleae Logic |
| Protocols | I2C, SPI, UART, CAN, USB, BLE, LoRa, Modbus |
| Testing | Unity (C test), Ceedling, Google Test (host-side) |

## Best Practices

- Hardware Abstraction Layer (HAL) to decouple logic from specific MCU.
- ISR should be minimal — set flag, enqueue, return. Process in task/main loop.
- Volatile for hardware registers and shared variables.
- Static allocation preferred over dynamic (no malloc in safety-critical code).
- Watchdog timer always enabled in production.
- Defensive programming: check all return codes, handle all error paths.
- Document pin assignments and peripheral usage in a central hardware map.
- Power management: sleep modes, clock gating, peripheral disable when idle.

## Anti-Patterns to Avoid

- Blocking delays in ISRs.
- Dynamic memory allocation in resource-constrained systems.
- Polling when interrupts/DMA are available and appropriate.
- Missing volatile on hardware registers.
- No watchdog — infinite loop hangs go undetected.
- Assuming endianness or struct packing across compilers.

## References

- `references/hardware-abstraction-guide.md` — HAL design patterns
- `references/debugging-embedded.md` — debugging tools and techniques
- `references/power-optimization.md` — power management strategies

## Expected Output Format

1. Working firmware with compilation for target platform
2. Memory usage report (RAM/Flash)
3. Pin/peripheral usage documentation
4. Test results (host-side unit tests + on-target verification)