# Anlogic Project Creation

> Use when Anlogic FPGA verification is already complete and Codex needs to create the TD project from validated design inputs, constraints, IP, and wrappers. This stage begins only after `anlogic-modelsim`, `anlogic-wave-signal-analyzer`, and `anlogic-signal-comparison` have produced a clean release conclusion.

- Skill: `folsie/anlogic-project-creation` (Agent Skill, multi-file: 12 files)
- Install (CLI): `npx skillmds@latest add folsie/anlogic-project-creation`
- Raw SKILL.md: https://api.skillmd.com/api/skills/folsie/anlogic-project-creation/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: folsie (https://skillmd.com/u/folsie)
- Updated: 2026-09-17
- Page: https://skillmd.com/skills/folsie/anlogic-project-creation

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# Anlogic FPGA TD Project Creation Skill

Use this skill only after the verification chain has released the design.

## Role

Turn validated design inputs into a synthesis-ready TD project without re-opening resolved verification decisions.

## Inputs

- the latest `doc/stage-S3-summary.md` and comparison release conclusion
- device, package, speed, constraints, IP, wrappers, and validated RTL inputs

## Boundaries

- do not redesign RTL architecture
- do not replace requirement analysis
- do not replace testbench or simulation release
- do not use project creation as a workaround for failed comparison

## Outputs

- synthesis-ready TD project input
- standard-directory mapping note when needed
- `doc/stage-S4-summary.md`

## Not Doing

- not reopening large historical layouts before checking indexes and stage summaries

## Upstream Inputs

Prefer inputs from:
- `anlogic-needs-analysis`: device, resources, interfaces, clocks, and primitive guidance
- `anlogic-python-signal-pre-research`: saved reference signal baseline
- `anlogic-code-design`: RTL structure and wrapper choices
- `anlogic-modelsim`: simulation conclusion and preserved waveform artifacts
- `anlogic-signal-comparison`: clean pass result

If the comparison gate has not passed, do not enter this stage.

## Responsibilities

- Create or copy the TD project
- Select device / package / speed
- Organize `.al` / `.prj`
- Import RTL, constraints, IP, wrappers, and include paths
- Prepare the project inputs for synthesis and later implementation
- Keep the standard root structure such as `doc/src/tb/msim/prj/bit/constrain`

## Not Responsible For

- Do not redesign RTL architecture
- Do not replace requirement analysis
- Do not replace testbench or simulation release
- Do not use project creation as a workaround for failed comparison

## Default Flow

1. Confirm `anlogic-signal-comparison` has passed.
2. Lock device, package, and speed grade.
3. Establish the project directory structure.
4. Clean only unrelated stale implementation leftovers that would pollute the current project audit.
5. Organize sources, constraints, IP, and wrappers.
6. Prepare the handoff to `anlogic-synthesis`.

## Gate Rules

- If requirement inputs are incomplete: go back to `anlogic-needs-analysis`
- If the reference baseline is missing or wrong: go back to `anlogic-python-signal-pre-research`
- If RTL or interfaces are still changing: go back to `anlogic-code-design`
- If simulation artifacts or comparison are not clean: go back to `anlogic-modelsim`, `anlogic-wave-signal-analyzer`, or `anlogic-signal-comparison`
- Only a clean comparison pass may release to this stage

## Strong Rules

- Use `constrain/` as the main constraints directory for new projects.
- Do not delete ModelSim artifacts such as `work/`, `transcript`, or `.wlf`; those remain owned by the simulation and waveform-analysis stages.
- Only clean unrelated stale implementation leftovers after confirming they are not part of the current verification evidence.

## Output Requirements

- valid TD project
- selected device / package / speed result
- source / constraint / IP / wrapper import result
- minimum synthesis-ready project input
- clear statement that the stage entered only after a clean `anlogic-signal-comparison` pass
- fixed summary fields:
  - `current_stage`
  - `goal`
  - `confirmed_constraints`
  - `artifacts`
  - `decision`
  - `blocking_reason`
  - `next_action`

## 2026-05-06 Rule: Hard-IP Identity And Legacy IP Compatibility

- Before importing DDR hard-IP assets, lock these identities explicitly:
  - board name
  - device and package
  - DDR generation
  - whether DDR IO is owned by hard-IP top-level connection rather than normal board ADC/SDC enumeration
- For AP111/AP110 class projects, do not treat DDR2 and DDR3 reference projects as drop-in interchangeable just because both are hard-IP based.
- If a legacy packaged IP fails inside encrypted or packaged vendor sources during project creation or first synthesis, prefer this order:
  1. regenerate the same hard IP with the matching TD version for the same target device/package
  2. only if regeneration is not available or still blocked, evaluate a same-device validated replacement asset
- Do not normalize "borrow IP from another project" as the default project-creation path; it is a fallback that must be called out as such in the stage conclusion.
- If a historical TD layout is preserved instead of the standard `doc/src/tb/msim/prj/bit/constrain` layout, add an explicit mapping note so later stages know where evidence and ownership live.