# Tb Creator

> 创建 SystemVerilog 测试平台文件。触发词包括：创建TB、写testbench、新建测试平台、生成TB、写TB、创建仿真测试文件

- Skill: `ljj05170930/tb-creator` (Agent Skill)
- Install (CLI): `npx skillmds@latest add ljj05170930/tb-creator`
- Raw SKILL.md: https://api.skillmd.com/api/skills/ljj05170930/tb-creator/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: ljj05170930 (https://skillmd.com/u/ljj05170930)
- Updated: 2026-09-17
- Page: https://skillmd.com/skills/ljj05170930/tb-creator

---


在 `TB/` 目录下创建 `TB/tb_top.sv`，直接使用模板，不询问任何参数。

## 文件模板

```systemverilog
// DUMP_ARRAY macro: per-element dumpvars for unpacked arrays
// gen_dumpvars.py --patch will auto-generate calls and insert them into the dump initial block below
`define DUMP_ARRAY(path, size) \
    begin \
        for (int _di = 0; _di < size; _di++) \
            $dumpvars(0, path[_di]); \
    end

`timescale 1ns/1ps

module tb_top;

// ── Parameters ────────────────────────────────────────────────────────
localparam CLK_PERIOD  = 10;    // clock period (ns), 100 MHz
localparam SIM_TIMEOUT = 10000; // simulation timeout (ns)
localparam RST_CYCLES  = 4;     // reset duration in cycles

// ── Clock & reset ─────────────────────────────────────────────────────
reg clk = 0;
reg rst_n;

always #(CLK_PERIOD/2) clk = ~clk;

initial begin
    rst_n = 0;
    repeat(RST_CYCLES) @(posedge clk);
    rst_n = 1;
end

// ── DUT instantiation (replace <dut_module> and port connections) ─────
// <dut_module> u_dut (
//     .clk   (clk  ),
//     .rst_n (rst_n)
// );

// ── Waveform dump (gen_dumpvars.py --patch will update this block) ────
initial begin
    $dumpfile("wave.fst");
    $dumpvars(0, tb_top);
end

// ── Simulation timeout ────────────────────────────────────────────────
initial begin
    #SIM_TIMEOUT;
    $display("[TIMEOUT] simulation exceeded %0d ns", SIM_TIMEOUT);
    $finish;
end

endmodule
```

## 执行步骤

1. 使用 Write 工具将上方模板写入 `TB/tb_top.sv`
2. 告知用户已创建 `TB/tb_top.sv`，提示下一步填写 DUT 实例化部分