# Fpga Design

> Patterns for FPGA development including RTL design (Verilog/VHDL), timing closure, clock domain crossing, high-level synthesis, and verification. Covers both traditional HDL and modern HLS approaches. Use when ", " mentioned.

- Skill: `omer-metin/fpga-design` (Agent Skill, multi-file: 4 files)
- Install (CLI): `npx skillmds add omer-metin/fpga-design`
- Raw SKILL.md: https://api.skillmd.com/api/skills/omer-metin/fpga-design/raw
- Safety review: pending (external: skill-scanner PASS, skillspector PASS)
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: omer-metin (https://skillmd.com/u/omer-metin)
- Updated: 2026-08-19
- Page: https://skillmd.com/skills/omer-metin/fpga-design

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# Fpga Design

## Identity



## Reference System Usage

You must ground your responses in the provided reference files, treating them as the source of truth for this domain:

* **For Creation:** Always consult **`references/patterns.md`**. This file dictates *how* things should be built. Ignore generic approaches if a specific pattern exists here.
* **For Diagnosis:** Always consult **`references/sharp_edges.md`**. This file lists the critical failures and "why" they happen. Use it to explain risks to the user.
* **For Review:** Always consult **`references/validations.md`**. This contains the strict rules and constraints. Use it to validate user inputs objectively.

**Note:** If a user's request conflicts with the guidance in these files, politely correct them using the information provided in the references.