# Fpga Synthesis Eval

> Evaluates trade-offs between inference latency and hardware resource utilization when deploying variational autoencoders on FPGAs using different synthesis frameworks (SNL vs. hls4ml) and quantization levels. Use when the user has predictions and gold and needs to compute Latency.

- Skill: `qhjqhj00/fpga-synthesis-eval` (Agent Skill)
- Install (CLI): `npx skillmds add qhjqhj00/fpga-synthesis-eval`
- Raw SKILL.md: https://api.skillmd.com/api/skills/qhjqhj00/fpga-synthesis-eval/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: AI & ML
- Author: qhjqhj00 (https://skillmd.com/u/qhjqhj00)
- Updated: 2026-09-08
- Page: https://skillmd.com/skills/qhjqhj00/fpga-synthesis-eval

---


# fpga-synthesis-eval

> Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition — Jia et al. (2024) (arXiv:2411.11678, 2024)

## What this evaluates

Evaluates trade-offs between inference latency and hardware resource utilization when deploying variational autoencoders on FPGAs using different synthesis frameworks (SNL vs. hls4ml) and quantization levels.

## Datasets

- **Benchmark VAE Models** — total 3; splits: benchmark (3)

## Metrics

- `Latency` **(primary)** — range: other
  - Measured inference runtime in microseconds after hardware synthesis on an Alveo U200 FPGA at a 200 MHz clock rate.
- `Resource Usage` — range: other
  - Counts of consumed hardware resources: Block RAMs, Digital Signal Processors, Flip-Flops, and Look-Up Tables on the target FPGA.

## Input / output format

**Input**: VAE model architecture specifications (layer node counts) and post-training quantization precision settings (ap_fix<32,16> or ap_fix<16,8>).

**Output**: Synthesis reports containing resource consumption counts (BRAM, DSPs, FFs, LUTs) and measured inference latency in microseconds for each synthesis strategy.

## Scoring recipe

```python
def evaluate_synthesis(synthesis_log, target_fpga_resources):
    latency_us = parse_latency(synthesis_log)
    resources = {
        'BRAM': parse_resource_count(synthesis_log, 'BRAM'),
        'DSPs': parse_resource_count(synthesis_log, 'DSPs'),
        'FFs': parse_resource_count(synthesis_log, 'FFs'),
        'LUTs': parse_resource_count(synthesis_log, 'LUTs')
    }
    out_of_resources = any(resources[k] > target_fpga_resources[k] for k in resources)
    return {'latency_us': latency_us, 'resources': resources, 'out_of_resources': out_of_resources}
```

## Common pitfalls

- Parallel vs. streaming data flow architectures differ between frameworks, making direct latency/resource comparisons sensitive to I/O configuration.
- Resource limits of the target FPGA (Alveo U200) can cause synthesis failures or out-of-resource errors for certain strategies/model sizes.
- Quantization precision (ap_fix) significantly impacts both latency and resource counts, requiring careful matching across strategies.

## Evidence (verbatim from paper)

> Results are given as comparisons of resource usage and latency for the FPGA inference runs between SNL and h1s4ml syntheses. The resources considered are those of a modern FPGA, specifically block random access memory (BRAM), digital signal processors (DSPs), flip-flops (FFs), and look-up tables (LUTs).

## Citation

```bibtex
@misc{jia2024fpgasynthesis,
  title={Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition},
  author={Jia et al. (2024)},
  year={2024},
  note={arXiv:2411.11678}
}
```

- arXiv: 2411.11678