# Hutch31 Tv80 Tv80

> Build TV80 Chisel Code

- Skill: `tomevault-io/hutch31-tv80-tv80` (Agent Skill, multi-file: 2 files)
- Install (CLI): `npx skillmds@latest add tomevault-io/hutch31-tv80-tv80`
- Raw SKILL.md: https://api.skillmd.com/api/skills/tomevault-io/hutch31-tv80-tv80/raw
- Safety review: pending (external: skill-scanner PASS, skillspector PASS)
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: tomevault-io (https://skillmd.com/u/tomevault-io)
- Updated: 2026-09-17
- Page: https://skillmd.com/skills/tomevault-io/hutch31-tv80-tv80

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# Build TV80 Chisel Code

## When to Use
- Compile and build the TV80 Chisel source files
- Generate Verilog output from Chisel RTL
- Check for Chisel/Scala compilation errors
- After editing any `.scala` file under `src/`

## Procedure

### Step 1 – Run the build
```pwsh
cd c:\Users\Guy\Documents\tv80
sbt "runMain tv80.tv80build"
```

### Step 2 – Check the output
- A successful build prints `[success]` at the end
- Errors include file name, line number, and message — fix them in the relevant `.scala` file
- Generated Verilog is written to the project root (or the path configured in the build main)

## Notes
- Run from the workspace root (`c:\Users\Guy\Documents\tv80`)
- Requires Java and sbt on PATH
- Chisel sources are under `src/main/scala/tv80/`
- Do **not** modify RTL files in `rtl/`

---
> Source: [hutch31/tv80](https://github.com/hutch31/tv80) — distributed by [TomeVault](https://tomevault.io).
<!-- tomevault:4.0:skill_md:2026-06-21 -->