# Mi300 Cdna3 Architecture

> MI300/CDNA3 architecture guide for HIP/Triton optimization—MFMA variants, dual register files, data formats, sparsity, LDS/GWS, and best practices.

- Skill: `wenyi-li/mi300-cdna3-architecture` (Agent Skill, multi-file: 2 files)
- Install (CLI): `npx skillmds@latest add wenyi-li/mi300-cdna3-architecture`
- Raw SKILL.md: https://api.skillmd.com/api/skills/wenyi-li/mi300-cdna3-architecture/raw
- Safety review: pending
- Works with: Claude Code, Claude.ai, OpenAI Codex
- Category: Coding & Dev Tools
- Author: wenyi-li (https://skillmd.com/u/wenyi-li)
- Updated: 2026-09-22
- Page: https://skillmd.com/skills/wenyi-li/mi300-cdna3-architecture

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# MI300 CDNA3 Architecture (Hardware Tuning Guide)

Use this when optimizing HIP/Triton kernels for MI300/CDNA3 hardware specifics.

Key points to remember (see reference for details):
- MFMA choices: pick variants by matrix size (small -> high block count like 4x4x1_16B; large -> bigger tiles). Use CBSZ/BLGP for broadcast/permutation.
- Dual register files: minimize VGPR↔AccVGPR traffic; keep hot accumulations in AccVGPR.
- Data formats: FP8/BF8 support, conversions/rounding; validate accuracy when using reduced precision.
- Structured sparsity: 4:2 pattern via SMFMAC; ensure encoding matches pattern to get gains.
- Memory: LDS bank-conflict avoidance; coalesced global buffer ops; use cache control bits (GLC/NV) and schedule loads early with `s_waitcnt`.
- Registers/occupancy: respect SGPR single-read limits; align VGPR usage; watch overall pressure to keep occupancy.
- Control/exec: wavefront characteristics, dependency scheduling; hide latency via instruction scheduling.
- Best practices section summarizes matrix, memory, register, and optimization checklists.

References:
- `references/AMD Instinct MI300 CDNA3 Architecture Guide for High-Quality HIP Kernel Development.md`