Soc Security

Use this skill when analyzing physical side-channel and fault injection attack surfaces — power analysis, electromagnetic emanation, voltage/clock/laser glitching, or combined attacks. Triggers on "DPA assessment", "fault injection resistance", "power side-channel review", "EM leakage analysis", "TVLA evaluation". Includes JIL scoring and ISO 17825 mapping. Do NOT use for microarchitectural side-channels (use microarch-attack-skill) or software-level isolation (use kernel-security-skill).

Use this skill when performing structured threat modeling for SoC hardware components — STRIDE analysis, attack tree construction, or standards-derived threat identification. Triggers on "threat model this block", "STRIDE analysis", "build an attack tree", "identify threats for". Covers Confidential AI, TDISP/CXL, Supply Chain, Secure Boot/DICE, and CHERI domains. Do NOT use for verification planning (use verification-scaffold-skill) or compliance tracking (use compliance-pipeline-skill).

Use this skill when translating technical security findings into executive communication — BLUF briefs, risk summary tables, or audience-adapted posture reports. Triggers on "executive summary of findings", "brief the CISO", "board-level security update", "summarize risks for leadership". Supports board, CISO, and program-level audiences. Do NOT use for technical analysis (use threat-model-skill or attack-domain specialists) or compliance tracking (use compliance-pipeline-skill).

Use this skill when analyzing kernel security at the hardware/software interface — memory management, process isolation, privilege escalation paths, or IOMMU/SMMU configuration. Triggers on "kernel hardening review", "IOMMU bypass analysis", "privilege escalation audit", "container escape assessment", "KASLR/KPTI evaluation". Do NOT use for microarchitectural attacks (use microarch-attack-skill) or physical side-channels (use physical-sca-skill).

Use this skill when analyzing microarchitectural attack surfaces — transient execution, cache side-channels, branch predictor attacks, or shared-resource contention. Triggers on "Spectre analysis", "cache side-channel review", "check for Meltdown variants", "microarchitectural isolation audit". Covers CPU/GPU/accelerator components. Do NOT use for physical side-channels (use physical-sca-skill) or kernel-level privilege escalation (use kernel-security-skill).

Use this skill when formalizing security properties into TLA+ specifications for model checking with TLC. Triggers on "formalize this security invariant", "TLA+ spec for this protocol", "model check this property", "write a TLA+ security spec". Translates threat findings and protocol behaviors into temporal logic. Do NOT use for threat identification (use threat-model-skill) or verification scaffolding without formal methods (use verification-scaffold-skill).

Use this skill when extracting requirements from security specifications, tracking compliance status, or producing gap analysis against hardware security standards. Triggers on "compliance check against DICE", "gap analysis", "extract requirements from spec", "FIPS compliance status", "ISO 21434 mapping". Covers DICE, TDISP, CXL, CHERI, SPDM, FIPS 140-3, and ISO 21434. Do NOT use for threat identification (use threat-model-skill) or executive communication (use executive-brief-skill).

Use this skill when analyzing emerging hardware security paradigms — post-quantum cryptography hardware, chiplet/UCIe architectures, heterogeneous compute, or AI accelerator security. Triggers on "PQC hardware review", "UCIe security assessment", "NPU memory isolation", "chiplet trust boundary analysis". Covers migration risk from classical to post-quantum or monolithic to chiplet. Do NOT use for established microarchitectural attacks (use microarch-attack-skill) or kernel-level analysis (use kernel-security-skill).

Use this skill when generating verification artifacts from threat findings — SVA assertion templates, security review checklists, or tiered verification plans. Triggers on "generate assertions for these threats", "verification checklist", "SVA template", "map threats to verification". Expects upstream ThreatFinding input. Do NOT use for threat identification (use threat-model-skill) or compliance gap analysis (use compliance-pipeline-skill).