Results for “verification-loop”

11 skills
More results
affaan-m
verification-loop
Runs a multi-phase verification pipeline including build, type-check, lint, tests, security scan, and diff review to ensure code quality before creating a PR.
226k
affaan-m
laravel-verification
Runs a multi-phase verification pipeline for Laravel projects including environment checks, linting, static analysis, tests with coverage, security scans, and deployment readiness.
226k
ai-builder-club
verifier-setup
Scaffolds a per-task verification skill for a repo, including a dev-local launcher, a browser driver, and a verification SOP that spawns a sub-agent to drive the app and produce proof.
770 · bundle
affaan-m
quarkus-verification
Runs a comprehensive verification pipeline for Quarkus projects including build, static analysis, tests with coverage, security scans, native compilation, and diff review before PRs or releases.
226k
affaan-m
django-verification
Runs a comprehensive verification pipeline for Django projects including migrations, linting, tests with coverage, security scans, and deployment readiness checks before PRs or releases.
226k
comeonoliver
cp
Verifies local changes, then commits and pushes the intended files on the current branch when explicitly requested.
61
samyakjhaveri
validate
Runs a two-wave validation pipeline (deterministic checks then rule-based checks) before every git commit, writing a sentinel file that a pre-commit hook enforces. Includes optional quick mode (first wave only) and a fix loop with up to three iterations.
0
ruslan-strazhnyk
form-validation-scan
Probe the forms on a page for validation gaps — missing required-field enforcement, no client-side validation, accepts malformed input, and absent error messaging. Reports per-field findings. Playwright MCP only, no signup.
matlab
matlab-deploy-embedded-code
Deploy MATLAB-generated code to embedded hardware using Embedded Coder. Use when configuring code generation for microcontrollers (STM32, Raspberry Pi, ARM Cortex), setting up PIL/SIL verification, disabling dynamic memory allocation, or configuring hardware-specific code generation settings. Covers ERT-based configurations, processor-in-the-loop testing, memory constraints, and the MEX→SIL→PIL verification progression.
920 · bundle