How do I install the Two Stage Opamp skill?

Run npx skillmds@latest add arcadia-1/two-stage-opamp in your terminal (requires Node.js), paste this page's agent-chat prompt into Claude, Cursor, or any MCP-connected agent, or download the SKILL.md file and copy it into your agent's skills directory.

Is Two Stage Opamp safe to use?

This skill has not completed SkillMD's automated safety review yet. SkillMD never runs a skill's scripts for you; review the SKILL.md before installing.

Which AI agents work with Two Stage Opamp?

This skill is tagged as working with Claude Code, Claude.ai, OpenAI Codex. SKILL.md is an open format, so most agents that read a skills directory can load it too.

Is Two Stage Opamp free to use?

Yes. Installing skills from SkillMD is free, and the skill stays under its author's original license.

Who published Two Stage Opamp?

arcadia-1 (@arcadia-1) published this skill. Their other Agent Skills are listed on their SkillMD profile.

Two Stage Opamp by arcadia-1 — Agent Skill

Name: Two Stage Opamp
Author: arcadia-1

Two Stage Opamp

Two-stage CMOS operational amplifier simulation skill. Use when the user wants to simulate or size a Miller-compensated two-stage op amp with PMOS differential input pair, NMOS current-mirror first-stage load, NMOS common-source second stage, PMOS current-source load, bias mirror, Cc compensation, and CL load. Supports ngspice DC operating point, AC gain/phase sweep, pole-zero analysis, and output-noise analysis.

arcadia-1 9b24450 20 files · 34.1 KB Updated Sep 17, 2026

File contents

Two-Stage Op Amp Skill

Miller-compensated two-stage CMOS op amp using PTM 180nm models.

Topology

M7 + Ibias -> PMOS bias mirror
M5        -> first-stage PMOS tail current source
M0, M1    -> PMOS differential input pair
M3, M4    -> NMOS current-mirror active load
M2        -> NMOS common-source second stage
M6        -> PMOS current-source second-stage load
Cc        -> Miller compensation from first-stage output to Vout
CL        -> output load capacitor

Ports: INP, INN, OUT, VDD, VSS.

Running

cd two_stage_opamp/scripts
python run_opamp.py

This runs:

DC operating point and basic bias currents.
AC open-loop gain and phase versus frequency.
Pole-zero extraction for dominant pole, non-dominant pole, and zeros.
Open-loop output-referred noise, input-referred noise, and unity-gain closed-loop output noise.

Outputs go to WORK/plots, WORK/logs, and WORK/netlists.

Main Scripts

Task	Script
Full simulation	`run_opamp.py`
DC operating point	`run_opamp_dc.py`
AC gain/phase	`run_opamp_ac.py`
Pole-zero	`run_opamp_pz.py`
Noise only	`run_opamp_noise.py`

Design Knobs

Edit scripts/opamp_common.py:

IBIAS controls the PMOS bias mirror current.
CC and CL set Miller compensation and output loading. The default CC=12pF is intentionally conservative so the extracted non-dominant pole and first RHP zero clear the GBW-ratio checks.
W_M0_M1_UM, W_M2_UM, W_M3_M4_UM, W_M5_M7_UM, W_M6_UM set transistor widths.
VCM sets input common-mode voltage.

---name: two-stage-opampdescription: Two-stage CMOS operational amplifier simulation skill. Use when the user wants to simulate or size a Miller-compensated two-stage op amp with PMOS differential input pair, NMOS current-mirror first-stage load, NMOS common-source second stage, PMOS current-source load, bias mirror, Cc compensation, and CL load. Supports ngspice DC operating point, AC gain/phase sweep, pole-zero analysis, and output-noise analysis.---# Two-Stage Op Amp SkillMiller-compensated two-stage CMOS op amp using PTM 180nm models.## Topology```textM7 + Ibias -> PMOS bias mirrorM5 -> first-stage PMOS tail current sourceM0, M1 -> PMOS differential input pairM3, M4 -> NMOS current-mirror active loadM2 -> NMOS common-source second stageM6 -> PMOS current-source second-stage loadCc -> Miller compensation from first-stage output to VoutCL -> output load capacitor```Ports: `INP`, `INN`, `OUT`, `VDD`, `VSS`.## Running```bashcd two_stage_opamp/scriptspython run_opamp.py```This runs:- DC operating point and basic bias currents.- AC open-loop gain and phase versus frequency.- Pole-zero extraction for dominant pole, non-dominant pole, and zeros.- Open-loop output-referred noise, input-referred noise, and unity-gain closed-loop output noise.Outputs go to `WORK/plots`, `WORK/logs`, and `WORK/netlists`.## Main Scripts| Task | Script ||------|--------|| Full simulation | `run_opamp.py` || DC operating point | `run_opamp_dc.py` || AC gain/phase | `run_opamp_ac.py` || Pole-zero | `run_opamp_pz.py` || Noise only | `run_opamp_noise.py` |## Design KnobsEdit `scripts/opamp_common.py`:- `IBIAS` controls the PMOS bias mirror current.- `CC` and `CL` set Miller compensation and output loading. The default `CC=12pF` is intentionally conservative so the extracted non-dominant pole and first RHP zero clear the GBW-ratio checks.- `W_M0_M1_UM`, `W_M2_UM`, `W_M3_M4_UM`, `W_M5_M7_UM`, `W_M6_UM` set transistor widths.- `VCM` sets input common-mode voltage.

Frequently asked questions