1---2name: rtl-p5s-integration-test3description: P5 Tier 4 integration tests: cross-module data flow, reset propagation, boundary handshakes. Triggers 'integration test', 'end-to-end system verification'.4---56<Purpose>7Run Tier 4 integration-level tests on the complete RTL system. Verifies cross-module interactions: data flows end-to-end with correct values, reset propagates to all sub-modules, clocks are connected correctly, and handshake protocols are observed across module boundaries. Outputs: `sim/top/integration_results.json` (per-test PASS/FAIL) and `reviews/phase-5-verify/integration-test-report.md`.8</Purpose>910<Use_When>11- All modules pass Tier 2 unit tests and Tier 3 module regression (PASS or PARTIAL_PASS).12- Cross-module interactions need verification (interface mismatches, protocol handshakes).13- Phase 5 integration verification step is required.14- Multi-module RTL changes may have affected interface compatibility.15</Use_When>1617<Do_Not_Use_When>18- Individual modules still fail Tier 2 unit tests — fix at Tier 2 first.19- Only single-module regression is needed — use `rtl-p5s-func-verify` (Tier 3).20- Performance measurement is the goal — use `rtl-p5s-perf-verify`.21- Standards conformance bitexact testing is needed — use `rtl-conformance-test`.22</Do_Not_Use_When>2324<Why_This_Exists>25Modules that pass individually may fail when connected due to interface mismatches, protocol violations, or timing assumptions that do not hold across boundaries. Integration testing catches: port width mismatches, reset not propagating to all sub-modules, backpressure not flowing through the pipeline, and data corruption at handoff points. These bugs are invisible to per-module testing.26</Why_This_Exists>2728## Prerequisites2930- All modules pass Tier 2 (`rtl-p4s-unit-test`) and Tier 3 (`rtl-p5s-func-verify`) — PASS or PARTIAL_PASS.31- RTL source files exist under `rtl/**/*.sv`.32- Phase 2 refC model output available as end-to-end reference oracle.3334If prerequisites are missing: WARNING — recommend completing Tier 2 and Tier 3 first. Orchestrator adapts scope with available artifacts.3536<Assets>37| Path | Role |38|------|------|39| `templates/integration-tb-template.sv` | Top-level integration TB scaffold: multi-module DUT instantiation, clock/reset generation, connectivity checker, data flow monitors. |40| `scripts/check_connectivity.py` | Static connectivity checker: parses top + submodule SV (ANSI headers), verifies named port connections, literal/parameter-resolvable width compatibility, dangling pins, and undriven top outputs; emits deterministic JSON violation report. |41| `references/integration-test-conventions.md` | Tier ordering, test categories, JSON schema, report structure, anti-patterns. |42| `examples/` | Worked example: `dut_top.sv` + 2 submodules with one intentional width mismatch and one dangling port, plus committed expected JSON — see `examples/README.md`. |43</Assets>4445<Responsibility_Boundary>46- **Scripts** handle deterministic checks: static connectivity analysis (port width/direction mismatches at module boundaries) before dynamic simulation is run.47- **LLM** handles interpretive analysis: handshake protocol observation, reset propagation verification narrative, and end-to-end reference comparison result interpretation.48- Contract surface: `integration_results.json` schema and test categories documented in `references/integration-test-conventions.md`.49</Responsibility_Boundary>5051<Execution>521. Read `references/integration-test-conventions.md` for Tier 4 context, test categories, JSON schema, and report structure.532. Spawn `p5s-integration-orchestrator` (see Tool_Usage) to run the full integration test suite.543. The orchestrator runs static connectivity checks first (`scripts/check_connectivity.py` — named connections, literal/parameter-resolvable widths, dangling pins, undriven top outputs; positional/`.*` connections and non-literal widths are flagged as unanalyzed, not guessed), then dynamic tests: data flow, reset propagation, handshake protocol, and end-to-end reference comparison using the Phase 2 refC model output as oracle.554. The orchestrator writes `sim/top/integration_results.json` with one entry per test case (category, verdict, failure detail).565. The orchestrator writes `reviews/phase-5-verify/integration-test-report.md` with the test results table, failure details (module boundary, signal path, first failure cycle), and a recommendation.576. Report the overall verdict and both output paths to the user.5859Apply steps 1-6 to every requested top-level module — do not stop after the first.60</Execution>6162<Tool_Usage>63Integration test orchestration:64```65Task(subagent_type="rtl-agent-team:p5s-integration-orchestrator",66 prompt="Execute Tier 4 integration testing. User input: $ARGUMENTS")67```6869Do not perform simulation work directly — the orchestrator manages connectivity checks, data flow tests, reset propagation tests, handshake verification, and end-to-end reference comparison.70</Tool_Usage>7172<Examples>73<example index="1">74<scenario>Video codec top-level after all per-module Tier 2 and Tier 3 tests pass; verifying the full encode pipeline end-to-end.</scenario>75<reference>examples/</reference>76<expected_output>Static connectivity check passes; all 5 data flow tests PASS; reset propagation PASS; end-to-end output matches refC oracle — overall PASS. Report recommends proceeding to final compliance and `rtl-p6-design-review`.</expected_output>77</example>7879<example index="2">80<scenario>AXI-Stream handshake fails at the boundary between the entropy coder and the bitstream packer due to a width mismatch.</scenario>81<reference>examples/</reference>82<expected_output>Static connectivity check reports `o_bin_val[7:0]` (cabac_encoder) connected to `i_data[15:0]` (bitstream_packer) — width mismatch. Dynamic simulation skipped. Report flags the boundary with signal paths; recommends Tier 2 re-run for both modules after RTL fix.</expected_output>83</example>8485<example index="3">86<scenario>Reset de-assertion reaches the top module but one sub-module never exits its reset state.</scenario>87<reference>examples/</reference>88<expected_output>Reset propagation test FAIL: `u_range_coder` remains in reset state 5 cycles after `sys_rst_n` de-asserts. `integration_results.json` records the failure with the first divergence cycle. Report identifies the missing reset connection in the instantiation.</expected_output>89</example>90</Examples>9192<Escalation_And_Stop_Conditions>93- Static connectivity check fails → report all width/direction mismatches; do not proceed to dynamic simulation.94- Individual modules still fail Tier 2 or Tier 3 → emit WARNING; integration results from pre-passing modules are not reliable.95- End-to-end reference comparison requires refC model output that is absent → note the missing oracle; mark `end_to_end` tests as `"verdict": "SKIP"` rather than fabricating comparison values.96- All dynamic tests pass but `end_to_end` fails → report FAIL; do not override with PARTIAL_PASS.97</Escalation_And_Stop_Conditions>9899## Output100101- `sim/top/integration_results.json` — per-test PASS/FAIL with category and failure details.102- `reviews/phase-5-verify/integration-test-report.md` — cross-module test results, failure signal paths, and recommendation.103104<Final_Checklist>105- [ ] Static connectivity check run before any dynamic simulation.106- [ ] All five test categories attempted: connectivity, data_flow, reset_propagation, handshake, end_to_end.107- [ ] `sim/top/integration_results.json` written with one entry per test.108- [ ] `reviews/phase-5-verify/integration-test-report.md` written with failure details and recommendation.109- [ ] End-to-end comparison uses Phase 2 refC model output as oracle — no fabricated reference values.110- [ ] RTL source not modified.111</Final_Checklist>
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