1. Naming Conventions
Class name = file name (one class per file). Protocol-level components use {proto}_, DUT-level
components use {module}_:
| Component |
Class / File Pattern |
Example |
| Agent / Driver / Monitor / Sequencer |
{proto}_agent etc. |
axi_agent, axi_driver, axi_monitor, axi_sequencer |
| Sequence Item |
{proto}_seq_item |
axi_seq_item |
| Sequence (base / specific) |
{proto}_base_seq / {proto}_{name}_seq |
axi_base_seq, axi_write_burst_seq |
| Scoreboard / Environment / Coverage |
{module}_scoreboard / {module}_env / {module}_coverage |
cabac_scoreboard, cabac_env |
| Test (base / specific) |
{module}_base_test / {module}_{name}_test |
cabac_base_test, cabac_smoke_test |
| Package |
{module}_tb_pkg.sv |
cabac_tb_pkg.sv |
| Top |
tb_{module}_top.sv |
tb_cabac_top.sv |
2. m_/u_ Prefix Boundary
- UVM class member handles use
m_ prefix (industry convention); the create() instance name
matches the variable name: m_driver = axi_driver::type_id::create("m_driver", this);
u_ prefix is for RTL module instances ONLY — including the DUT instance in the TB top (u_dut)
3. RTL Port-Name Matching
TB interfaces/signals connect to DUT ports using the RTL names verbatim: i_/o_/io_ prefixes,
clk/{domain}_clk, rst_n/{domain}_rst_n (e.g., @(posedge vif.sys_clk)). Never invent
TB-side port aliases.
4. Anti-Patterns
| Anti-Pattern |
Problem |
Fix |
| Not registered with factory |
Cannot override/reuse |
Add uvm_*_utils to all classes |
| Objection in driver |
Phase control confusion |
Only raise/drop in test |
| Ignoring config_db get failure |
Null pointer crash |
Handle with uvm_fatal |
| Direct DUT access from sequence |
Destroys reusability |
Use sequencer→driver path only |
| Hard-coded hierarchy path |
Destroys portability |
Use config_db wildcard |
#delay in run_phase |
Destroys portability |
Use @(posedge vif.sys_clk) |
1---2name: uvm3description: uvm project conventions (loaded by writer agents; do not invoke).4---56<Purpose>7UVM project conventions (naming + RTL boundary rules) for UVM testbench work.8Base: IEEE 1800.2-2020 UVM standard — standard UVM mechanics (factory registration, phasing,9TLM ports, config_db, sequences, objections) are assumed known and are not restated here.10</Purpose>1112<Use_When>13- Writing UVM testbenches, agents, sequences, or scoreboards (Phase 5, `rtl-p5s-uvm-verify`)14- Agents: testbench-dev15</Use_When>1617<Do_Not_Use_When>18- cocotb Python verification → `rtl-p5s-func-verify` skill; SVA-only work → `systemverilog-assertion` skill; synthesizable RTL → `systemverilog` skill19</Do_Not_Use_When>2021<Execution_Policy>22- Environment scaffold: `templates/uvm-env-template.sv`; smoke test structure: `examples/uvm-smoke-test-example.sv`23- All UVM classes registered with the factory; objections raised/dropped only in the test24</Execution_Policy>2526<Steps>2728## 1. Naming Conventions2930Class name = file name (one class per file). Protocol-level components use `{proto}_`, DUT-level31components use `{module}_`:3233| Component | Class / File Pattern | Example |34|-----------|---------------------|---------|35| Agent / Driver / Monitor / Sequencer | `{proto}_agent` etc. | `axi_agent`, `axi_driver`, `axi_monitor`, `axi_sequencer` |36| Sequence Item | `{proto}_seq_item` | `axi_seq_item` |37| Sequence (base / specific) | `{proto}_base_seq` / `{proto}_{name}_seq` | `axi_base_seq`, `axi_write_burst_seq` |38| Scoreboard / Environment / Coverage | `{module}_scoreboard` / `{module}_env` / `{module}_coverage` | `cabac_scoreboard`, `cabac_env` |39| Test (base / specific) | `{module}_base_test` / `{module}_{name}_test` | `cabac_base_test`, `cabac_smoke_test` |40| Package | `{module}_tb_pkg.sv` | `cabac_tb_pkg.sv` |41| Top | `tb_{module}_top.sv` | `tb_cabac_top.sv` |4243## 2. m_/u_ Prefix Boundary4445- UVM class member handles use `m_` prefix (industry convention); the `create()` instance name46 matches the variable name: `m_driver = axi_driver::type_id::create("m_driver", this);`47- `u_` prefix is for RTL module instances ONLY — including the DUT instance in the TB top (`u_dut`)4849## 3. RTL Port-Name Matching5051TB interfaces/signals connect to DUT ports using the RTL names verbatim: `i_`/`o_`/`io_` prefixes,52`clk`/`{domain}_clk`, `rst_n`/`{domain}_rst_n` (e.g., `@(posedge vif.sys_clk)`). Never invent53TB-side port aliases.5455## 4. Anti-Patterns5657| Anti-Pattern | Problem | Fix |58|-------------|---------|-----|59| Not registered with factory | Cannot override/reuse | Add `uvm_*_utils` to all classes |60| Objection in driver | Phase control confusion | Only raise/drop in test |61| Ignoring config_db get failure | Null pointer crash | Handle with `uvm_fatal` |62| Direct DUT access from sequence | Destroys reusability | Use sequencer→driver path only |63| Hard-coded hierarchy path | Destroys portability | Use config_db wildcard |64| `#delay` in run_phase | Destroys portability | Use `@(posedge vif.sys_clk)` |6566</Steps>6768<Tool_Usage>69This skill is not executed directly. It is referenced by agents that generate UVM environments70(e.g., testbench-dev). Agents should follow the conventions defined here.71</Tool_Usage>7273<Examples>74Environment structure with factory/naming/config_db patterns: `templates/uvm-env-template.sv`.75Smoke test structure: `examples/uvm-smoke-test-example.sv`.76</Examples>7778<Escalation_And_Stop_Conditions>79- UVM environment compilation error → request fix from testbench-dev80- Coverage target not met → write additional sequences or request analysis from coverage-analyst81- Scoreboard mismatch → request RTL vs Ref Model comparison from func-verifier82</Escalation_And_Stop_Conditions>8384<Final_Checklist>85- [ ] All UVM classes registered with factory (`uvm_component_utils` / `uvm_object_utils`)86- [ ] Objection raised/dropped only in test87- [ ] `uvm_fatal` on config_db get failure88- [ ] TLM analysis port connects monitor→scoreboard89- [ ] Virtual interface passed via config_db90- [ ] Naming convention: `{proto}_agent`, `{proto}_driver`, `m_` prefix instances91- [ ] Coverage collector subscribes to analysis port92- [ ] Port names match RTL (sys_clk, sys_rst_n, i_/o_)93</Final_Checklist>
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