dingxingdi Skill: constraint-driven modular-template-synthesis
1. Capability Definition & Real Case
- Professional Definition: The ability to perform grounded synthesis of complex composite systems by mapping high-level functional specifications and quantitative constraints (e.g., PPA budgets—Power, Performance, Area) to discrete modular components within a specialized library. This involves identifying the optimal configuration of parameters (systolic size, bit-width, arithmetic logic type) through a retrieval-augmented loop that assembles dependent sub-modules into a logically consistent architectural hierarchy.
- Dimension Hierarchy: Specialized Knowledge Navigation->Corpus-Specific Retrieval & Reasoning->constraint-driven modular-template-synthesis
Real Case
[Case 1]
- Initial Environment: A RAG library containing highly-parameterized RTL code for 13 approximate adders and 12 approximate multipliers, indexed with their corresponding Power, Performance, and Area (PPA) metrics for a 45nm technology library.
- Real Question: Generate the top-level Verilog code for a 4x4 TPU systolic array using HERLOA approximate adders and BAM multipliers with a weight width of 8 bits. The total area should not exceed 30,000 square microns.
- Real Trajectory: 1. Extract design parameters: Size=4x4, Adder=HERLOA, Multiplier=BAM, WW=8. 2. Retrieve PPA metrics for the 4x4 BAM+HERLOA configuration from the metadata-augmented dataset. 3. Verify total predicted area (29,162 sq microns) against the constraint (30,000). 4. Access the Verilog template library to fetch the 'HERLOA' and 'BAM' module definitions. 5. Synthesize the top-level Verilog file by instantiating the 4x4 grid and wiring the retrieved approximate MAC units to the IO buffers.
- Real Answer: A complete, synthesizable Verilog top-module file that correctly instantiates 16 APEs (Approximate Processing Elements) with the specified HERLOA/BAM configurations.
- Why this demonstrates the capability: The agent must perform a multi-step mapping from a verbal budget constraint to a specific set of modular indices in the knowledge base. It avoids 'hallucinated variables' by grounding the instantiation in the actual available library modules revealed during the retrieval phase.
[Case 2]
- Initial Environment: An architectural corpus providing a generic template for Tensor Processing Units (TPUs) alongside 25,000 distinct configuration headers and their validated PPA impact reports.
- Real Question: I need a specialized accelerator for ResNet18 inference on CIFAR-10. What is the most power-efficient multiplier choice available in the library for this workload, and give me the instantiation code?
- Real Trajectory: 1. Analyze the ResNet18/CIFAR-10 workload requirements for bit-precision (DW:8). 2. Scan the PPA database for 8-bit multipliers with the lowest 'Total Power' metric. 3. Identify 'DRALM' (Dynamic Range Approximate Logarithmic Multiplier) as the optimal choice. 4. Retrieve the RTL dependency file for the DRALM module. 5. Generate the top-level configuration header that sets
define DW 8anddefine DRALMto satisfy the power-efficient intent. - Real Answer: DRALM (Total Power: 4.21e-03 mW) with associated HDL implementation.
- Why this demonstrates the capability: This case requires 'analytical retrieval' to satisfy a qualitative goal ('most power-efficient') by comparing quantitative metrics across a large retrieved population, then performing a code-instantiation synthesis step.
Pipeline Execution Instructions
To synthesize data for this capability, you must strictly follow a 3-phase pipeline. Do not hallucinate steps. Read the corresponding reference file for each phase sequentially:
Phase 1: Environment Exploration Read the exploration guidelines to discover raw knowledge seeds:
references/EXPLORATION.mdPhase 2: Trajectory Selection Once Phase 1 is complete, read the selection criteria to evaluate the trajectory:
references/SELECTION.mdPhase 3: Data Synthesis Once a trajectory passes Phase 2, read the synthesis instructions to generate the final data:
references/SYNTHESIS.md