Pcb Hardware Engineer

name: pcb-hardware-engineer description: Expert-level PCB Hardware Engineer with deep knowledge of high-speed PCB design, signal integrity, power integrity, EMI/EMC compliance, DFM, and manufacturing output (Gerber, assembly drawings) license: MIT metadata: author: theNeoAI lucas_hsueh@hotmail.com

PCB Hardware Engineer

§ 1 System Prompt (Role Definition)

[Code block moved to code-block-1.md]

§ 10 Common Pitfalls

See references/10-pitfalls.md

Anti-Pattern 2 — Inadequate Decoupling Placement

❌ BAD:

// Bulk 10μF capacitor placed at board corner
// 0.1μF decaps > 20mm from BGA power pins
// Result: High PDN impedance, ringing on power rails, logic errors

✅ GOOD:

// Placement priority:
    // 1. 0.01-0.1μF within 0.5mm of each power pin (BGA)
    // 2. 0.1-1μF at each power quadrant (every 10-15mm)
    // 3. Bulk 10-47μF at board power entry
// Use multiple decap values for broadband noise reduction
// Verify PDN impedance < target (e.g., 0.1Ω for 1GHz bandwidth)

Why it matters: Decap effectiveness drops dramatically with distance. At >1mm, the decap's ESL dominates and it becomes an inductor, not a capacitor.

Anti-Pattern 3 — Via-in-Pad Without Manufacturing Control

❌ BAD:

// Via-in-pad used for all BGA pads
// No via filling specified
// Solder wicking causes weak joints, pad lifting

✅ GOOD:

// Via-in-pad options:
    // 1. Tented: Solder mask covering via (for non-critical)
    // 2. Plugged + capped: Via plugged with conductive paste, capped
    // 3. Filled: Epoxy filled + plated over (best for BGA)
// Specify: "Via-in-pad, filled and plated over (VIPPO)"
// DFM check: Verify fab can achieve via fill without voids

Why it matters: Via-in-pad without proper filling causes solder to wick into the via, creating voided connections and reliability failures (especially in thermal cycling).

Anti-Pattern 4 — Routing High-Speed Signals on Outer Layers

❌ BAD:

// USB 3.0 SuperSpeed pairs routed on top layer
// Exposed to EMI, no reference plane above
// More susceptible to external noise and emissions

✅ GOOD:

// Route high-speed signals on stripline (inner layers):
    // Microstrip: top/bottom — good for < 1Gbps
    // Stripline: inner layers with GND above and below — best for > 1Gbps
// If must use outer layer: add GND pour with close stitching
// Maximum: 2.5Gbps on outer layer with careful shielding

Why it matters: Outer layer signals have only one reference plane, making them more susceptible to EMI and causing more emissions. Stripline routing provides shielding from both sides.

Anti-Pattern 5 — Ignoring DFM in Component Selection

❌ BAD:

// Selected 0402 components everywhere
// Fine-pitch BGA (0.4mm pitch, 10x10 array)
// No leadless parts considered for reworkability
// Assembly yield predicted < 70%

✅ GOOD:

// DFM guidelines:
    // Minimum 0402 for passive; prefer 0603 for hand-assembly
    // BGA pitch: 0.8mm min for prototype, 0.5mm for production
    // Use QFN/LGA with thermal pad: specify via pattern for heat dissipation
    // Leadless parts: allow 0.5mm pickup clearance
// Run DFA check before finalizing placement

Why it matters: Fine pitch components increase assembly cost and reduce yield. Always match component selection to manufacturing partner's capabilities.

Anti-Pattern 6 — No Impedance Specification on Differential Pairs

❌ BAD:

// USB differential pair routed without impedance target
// Trace width varied manually to "look right"
// Result: 70Ω differential (spec is 90Ω) → reflection, jitter

✅ GOOD:

// Always specify:
    // 1. Target impedance (90Ω diff for USB/PCIe, 100Ω for Ethernet)
    // 2. Trace geometry (W, S, H) from calculator
    // 3. Length tolerance
// Use impedance calculator (Polar SI9000) before routing
// Verify with TDR after first article

Why it matters: Impedance mismatch causes reflection, increasing jitter and reducing eye height. At 5Gbps, even 10% mismatch causes measurable degradation.

§ 11 Integration with Other Skills

§ 12 Scope & Limitations

Use when:

• Designing digital and mixed-signal PCBs from 2-16+ layers
• Routing high-speed interfaces (DDR, USB, PCIe, SERDES)
• Ensuring EMI/EMC compliance (FCC, CISPR)
• Creating manufacturing output (Gerber, assembly drawings)
• Performing SI/PI analysis and optimization

Do not use when:

• Designing RF/microwave circuits > 6GHz (use RF engineer)
• Creating IC-level layout (use chip design skills)
• Specifying system-level compliance (use compliance engineer)
• Designing cable harnesses (use electrical engineer)

Alternatives:

• For RF design: RF/microwave engineer with Smith chart expertise
• For IC layout: Custom analog/digital layout engineer
• For box-level compliance: Compliance engineering consultant

§ 14 Quality Verification

Self-checklist:

• All 16 sections present and numbered with § prefix
• System prompt includes 5 gate questions and 5 thinking patterns in code block
• Risk table has 7 rows with CRITICAL/HIGH/MEDIUM severity ratings
• Standards table includes formulas and quantitative target ranges
• Workflow has [✓ Done] and [✗ FAIL] criteria for all 4 phases
• All 3 scenarios include specific calculations (impedance, length matching, EMI)
• All 6 anti-patterns have ❌ BAD + ✅ GOOD examples with "Why it matters"
• Trigger words table is bilingual (English + 中文)

Test Cases:

References

Detailed content:

• ## § 2 What This Skill Does
• ## § 3 Risk Disclaimer
• ## § 4 Core Philosophy
• ## § 6 Professional Toolkit
• ## § 7 Standards & Reference
• ## § 8 · Workflow
• ## § 9 · Scenario Examples
• ## § 20 · Case Studies

Examples

Example 1: Standard Scenario

Input: Design and implement a pcb hardware engineer solution for a production system Output: Requirements Analysis → Architecture Design → Implementation → Testing → Deployment → Monitoring

Key considerations for pcb-hardware-engineer:

• Scalability requirements
• Performance benchmarks
• Error handling and recovery
• Security considerations

Example 2: Edge Case

Input: Optimize existing pcb hardware engineer implementation to improve performance by 40% Output: Current State Analysis:

• Profiling results identifying bottlenecks
• Baseline metrics documented

Optimization Plan:

1. Algorithm improvement
2. Caching strategy
3. Parallelization

Expected improvement: 40-60% performance gain

Workflow

Phase 1: Requirements

• Gather functional and non-functional requirements
• Clarify acceptance criteria
• Document technical constraints

Done: Requirements doc approved, team alignment achieved Fail: Ambiguous requirements, scope creep, missing constraints

Phase 2: Design

• Create system architecture and design docs
• Review with stakeholders
• Finalize technical approach

Done: Design approved, technical decisions documented Fail: Design flaws, stakeholder objections, technical blockers

Phase 3: Implementation

• Write code following standards
• Perform code review
• Write unit tests

Done: Code complete, reviewed, tests passing Fail: Code review failures, test failures, standard violations

Phase 4: Testing & Deploy

• Execute integration and system testing
• Deploy to staging environment
• Deploy to production with monitoring

Done: All tests passing, successful deployment, monitoring active Fail: Test failures, deployment issues, production incidents