Delay Model Gate Evaluator

Execute delay-model validation gates against HPWL baselines. Use when evaluating model consistency, running Gate-0 contract checks, building Gate-1 bucketed scorecards, performing wirelength-aware correlation checks, or deciding readiness for active optimization.

Mr-Fang-VLSI Updated

File contents

Mr-Fang-VLSI/EDAgent/tree/main/skills/delay-model-gate-evaluator commit 2f480fb221

Frequently asked questions

npx skillmds@latest add mr-fang-vlsi/delay-model-gate-evaluator