Assembly X86

x86-64 assembly

GCC and Clang emit AT&T syntax by default. This skill reads that output, writes inline asm, and keeps register use inside the System V AMD64 ABI.

Contract

Inputs

• The C or C++ source, compiler output, or assembly fragment: required.
• The compiler: required. AT&T versus Intel output and inline asm details follow it.
• The ABI: required. System V for Linux and macOS; the Microsoft x64 ABI changes the register map entirely.

Procedure

1. Generate the baseline. Read the compiler's own output before writing any. Done when: the disassembly of the function under discussion is on screen.

gcc -O2 -S -fverbose-asm foo.c -o foo.s
gcc -O2 -c foo.c -o foo.o && objdump -d -M intel foo.o

2. Map registers by role. Done when: every register in the fragment is classified.

System V argument order: integer and pointer args in rdi, rsi, rdx, rcx, r8, r9, then the stack; float and vector args in xmm0 to xmm7.

3. Respect the stack rules. rsp stays 16-byte aligned before a call, because the call pushes 8 bytes and the callee expects alignment. The red zone is the 128 bytes below rsp that leaf functions may use without adjusting rsp. Kernel code compiles with -mno-red-zone because interrupts do not honor it. Done when: the drafted prologue keeps the alignment and names the red-zone choice.

push rbp
mov  rbp, rsp
sub  rsp, 16        # keep rsp a multiple of 16 before call sites

4. Read the recurring instruction shapes. Done when: each line in the fragment parses.

5. Choose a syntax and stay in it. AT&T puts the source operand first and prefixes registers and immediates; Intel puts the destination first. Done when: the listing and the written code use one syntax.

6. Write inline asm with the extended syntax. The template lists outputs, inputs, and clobbers. Constraint codes: r general register, a/b/c/d specific ones, m memory, i immediate. Tell the compiler about memory effects with "memory". Done when: the fragment compiles and survives optimization with correct results.

static inline long cpuid_leaf(long leaf) {
    long a, b, c, d;
    __asm__ volatile("cpuid"
                     : "=a"(a), "=b"(b), "=c"(c), "=d"(d)
                     : "a"(leaf));
    return a;
}

static inline int atomic_incr(int *p) {
    int ret;
    __asm__ volatile("lock xaddl %0, %1"
                     : "=r"(ret), "+m"(*p)   // +m: read and written
                     : "0"(1));
    return ret;   // returns the previous value
}

7. Recognize the SSE and AVX headers when reading vector code. <xmmintrin.h> provides SSE, <emmintrin.h> SSE2, and <immintrin.h> everything through AVX-512. For choosing and writing intrinsics use simd-intrinsics. Done when: vector code under discussion is attributed to its instruction set level.

Failure and recovery

Output

Annotated assembly or inline asm with register roles, stack alignment stated, and clobbers justified. The full instruction tables, flags register map, conditional jump list, and prologue patterns are in references/reference.md.