Comet Thermal Sim Eval

comet-thermal-sim-eval

CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems — Lokesh Siddhu et al. (arXiv:2109.12405, 2021)

What this evaluates

Evaluates the accuracy and overhead of an integrated thermal simulation toolchain (CoMeT) for modeling processor-memory thermal dynamics across 2D, 2.5D, and 3D architectures. It probes the tool's ability to capture thermal coupling, leakage power effects, and DVFS/DTM interactions under diverse compute and memory-intensive workloads.

Datasets

• PARSEC 2.1 — total ?; splits: test (-1)
• SPLASH-2 — total ?; splits: test (-1)
• SPEC CPU2017 — total ?; splits: test (-1)

Metrics

• Temperature (primary) — range: other
  • Peak and average temperature recorded per core and memory layer over 1 ms simulation epochs. Computed from thermal simulation output.
• Simulation Time Overhead — range: percent
  • Percentage increase in total simulation runtime compared to the HotSniper baseline: ((CoMeT_time - HotSniper_time) / HotSniper_time) * 100.
• Execution Time — range: other
  • Wall-clock time to complete benchmark instructions or normalized speedup relative to baseline configurations.

Input / output format

Input: Pre-compiled benchmark source code (PARSEC, SPLASH-2) or Pinballs traces (SPEC CPU2017, 100M instructions) mapped onto configurable core-memory floorplans (2D-ext, 3D-ext, 2.5D, 3D-stacked).

Output: Time-series temperature traces per core/memory layer, power dissipation values, execution times, and normalized simulation runtime.

Scoring recipe

1. Run benchmark on CoMeT with specified architecture config.
2. Record temperature, power, and execution time at each 1ms epoch.
3. Compute average/peak temperature across all layers.
4. Compare CoMeT runtime to HotSniper runtime: overhead = ((CoMeT_time - HotSniper_time) / HotSniper_time) * 100.
5. Report normalized speedup relative to 4-core baseline.

Common pitfalls

• Assuming core temperature is always the system hotspot; memory layers can be significantly hotter due to stacking and leakage power.
• Confusing the four core-memory topologies (2D-ext, 3D-ext, 2.5D, 3D-stacked) which have distinct thermal coupling characteristics.
• Ignoring thermal hysteresis and delay in DVFS/DTM response when memory hotspots are far from core layers.

Evidence (verbatim from paper)

We use a diverse set of workloads namely, PARSEC 2.1 [4], SPLASH-2 [55] and SPEC CPU2017 [9] to study the performance, power, and thermal profiles for core and memory. ... Thermal simulation is invoked periodically with an epoch time of 1 ms. ... We observe that the cores have relatively lower temperatures than memory banks due to the memory-intensive nature of the lbm benchmark.

Citation

@misc{siddhu2021comet,
  title={CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems},
  author={Lokesh Siddhu et al.},
  year={2021},
  note={arXiv:2109.12405}
}

• arXiv: 2109.12405