Fpga Hardware Latency Efficiency

fpga-hardware-latency-efficiency

Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators — Zhang et al. (2025) (arXiv:2511.17971, 2025)

What this evaluates

Evaluates the end-to-end inference and training latency, power consumption, and energy efficiency of a tensorized neural network hardware accelerator on an FPGA platform, comparing against baseline and prior FPGA accelerators.

Datasets

• CIFAR-10 — total ?; splits: test (-1)
• Tiny ImageNet — total ?; splits: test (-1)

Metrics

• Latency (ms) (primary) — range: ms
  • End-to-end execution time for inference or training measured via systolic array simulator and FPGA HLS synthesis.
• Power (W) — range: W
  • Average power consumption during execution measured on the target FPGA device.
• Energy Efficiency (GOPS/W) (primary) — range: other
  • Giga Operations Per Second divided by Power consumption in Watts, measuring computational throughput per unit of energy.

Input / output format

Input: Neural network models (ResNet-18, ViT-Ti/4) and datasets (CIFAR-10, Tiny ImageNet) with INT8 quantized parameters, activations, and gradients, mapped to configurable FPGA hardware settings (core partitioning, contraction paths, dataflow mappings).

Output: Execution latency in milliseconds, power consumption in Watts, FPGA resource counts (BRAM, FF, LUT, DSP), and energy efficiency in GOPS/W.

Scoring recipe

def compute_metrics(model, dataset, config):
    latency_ms = measure_execution_time(model, dataset, config)
    power_w = measure_power_consumption(model, dataset, config)
    gops = compute_giga_operations(model, dataset)
    efficiency = gops / power_w
    return latency_ms, power_w, efficiency

Common pitfalls

• Assuming the tensor contraction path with the lowest theoretical MAC count yields the lowest hardware latency; dataflow and core partitioning heavily impact actual latency.
• Comparing results across different prior works without normalizing for dataset, device, and precision; the paper notes direct apples-to-apples comparisons are infeasible except on ResNet-18 on CIFAR-10 INT8.

Evidence (verbatim from paper)

Within this widely used evaluation setting, our design achieves a peak energy efficiency of 19.19 GOPS/W in INT8 precision on the VU9P device, delivering 1.27× and 2.13× higher efficiency than (guo2023boost) and (venkataramanaiah2020fpga), respectively, while maintaining moderate BRAM (1482) and DSP (1024) usage.

Citation

@misc{zhang2025comprehensive,
  title={Comprehensive Design Space Exploration for Tensorized Neural Network Hardware Accelerators},
  author={Zhang et al. (2025)},
  year={2025},
  note={arXiv:2511.17971}
}

• arXiv: 2511.17971