Snn Dfe Optical Eval

snn-dfe-optical-eval

Efficient FPGA Implementation of an Optimized SNN-based DFE for Optical Communications — Moursi et al. (2024) (arXiv:2409.08698, 2024)

What this evaluates

Evaluates the communication performance and hardware efficiency of Spiking Neural Network-based Decision-Feedback Equalizers (DFEs) for optical channels compared to traditional Artificial Neural Network baselines. It probes the trade-off between bit error rate, computational complexity, and energy efficiency under varying quantization levels and FPGA resource constraints.

Datasets

• Custom Optical Communication DFE Benchmark — total ?; splits: test (-1)

Metrics

• BER (primary) — range: [0, 1]
  • Bit Error Rate calculated as the ratio of incorrectly decoded bits to the total number of transmitted bits over the evaluation set.
• Energy Efficiency (pJ/MAC) — range: other
  • Dynamic energy consumption per multiply-accumulate operation, computed by dividing the total dynamic energy (in microjoules) by the total MAC operations and scaling to picojoules.

Input / output format

Input: Optical channel signal samples processed in burst mode (1000 samples per cycle).

Output: Equalized signal decisions / bit estimates per sample.

Scoring recipe

# Bit Error Rate (BER)
total_bits = len(predictions)
errors = sum(1 for p, g in zip(predictions, gold) if p != g)
ber = errors / total_bits

# Energy Efficiency (pJ/MAC)
dynamic_energy_uj = dynamic_power_w * latency_ns / 1e3
mac_ops = count_mac_operations()
energy_efficiency = (dynamic_energy_uj * 1e3) / mac_ops

Common pitfalls

• Comparing topologies without first adjusting input/output parallelism to match throughput, leading to unfair latency and power comparisons.
• Confusing static PL power with dynamic power when calculating energy efficiency, as static power does not scale with processing cycles.
• Ignoring the impact of quantization-aware training (QAT) bit-width on BER, as 4-bit and 6-bit variants show significant performance drops compared to 8-bit.

Evidence (verbatim from paper)

We run each topology for 100K cycles, in each cycle 1000 samples are processed in burst mode. We measured the latency and power of the PL and averaged them over the total number of samples. The power of the PL is composed of two components, a static component and a dynamic component. Static power is the power consumed by the PL without stimulating any input, while dynamic power is consumed while stimulating input. Comparing ANN_ref with SNN_ref we see that SNN_ref requires 2.86× more power while its dynamic energy is higher by a factor of 9.52. On the other side, SNN_72 requires a total power that is higher than ANN_ref by 1.16× while having almost the same dynamic energy. With respect to the energy efficiency we see that the unoptimized SNN_ref already has 9.6× better energy efficiency compared to ANN_ref ; while SNN_72 pushes this number even further to 25× .

Citation

@misc{moursi2024efficientfpga,
  title={Efficient FPGA Implementation of an Optimized SNN-based DFE for Optical Communications},
  author={Moursi et al. (2024)},
  year={2024},
  note={arXiv:2409.08698}
}

• arXiv: 2409.08698