Caiyujie007
- 9 skills
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- 11 hours ago last updated
- ▌ Drawio · caiyujie007 bundleCreate, edit, replicate, import, and export draw.io diagrams with an offline YAML-first workflow. Use for general engineering and product diagrams: architecture, network topologies, flowcharts, UML/ER, org charts, Mermaid/CSV conversion, existing .drawio bundles, style presets, themes, and non-publication formula diagrams. For paper, thesis, journal, conference, IEEE/ACM, manuscript, camera-ready, or publication figures, prefer drawio-academic-skills; this base provides shared CLI, references, themes, schemas, styles, and optional Desktop export.
- ▌ Flexnoc Diagram · caiyujie007 bundle使用中文流程提取 FlexNoC 生成 RTL 的 NoC Req/Resp 结构关系，并基于 Req.md、Resp.md 与 draw.io 绘制 NoC 架构图。用于用户要求分析 FlexNoC NoC 拓扑、master/slave NIU、switch req/resp 模块、flit 连接关系、Req/Resp 网络或生成 draw.io/SVG/PNG 架构图时。
- ▌ Vivado Workflow · caiyujie007Xilinx Vivado tool workflow for project-mode RTL synthesis with preserved Vivado projects, DRC/timing/utilization reports, xvlog/xelab/xsim simulation, WDB waveform database generation and scripted querying, WCFG waveform view generation or cleanup, and Vivado Tcl automation. Use only when the task explicitly involves Vivado, xsim, xvlog, xelab, WDB, WCFG, Vivado Tcl, Vivado project-mode synthesis, or Vivado reports; pair with circuit-design-verification for tool-independent verification methodology.
- ▌ Rtl Open Tools Flow · caiyujie007Open-source RTL checking and simulation workflow using Verilator, Yosys, Icarus Verilog, and GTKWave. Use when Codex needs to run or set up lightweight RTL syntax/lint checks, Yosys structural sanity checks, Icarus Verilog simulations, VCD/GTKWave waveform handoff, macOS Homebrew installation notes for these tools, or a reproducible open-source verification flow; pair with circuit-design-verification for tool-independent RTL intent and debugging methodology. Do not use for Vivado/xsim/WDB/WCFG flows.
- ▌ Flexnoc Flit Monitor · caiyujie007 bundle生成 FlexNoC Req 网络 flit monitor 调试包。Use when Codex needs to create Verilog monitor RTL, an include template, and a Verdi/nWave rc file from a FlexNoC top RTL, monitor instance path, and Req.md Record table, especially for observing Req flit state, seqid, master attribution, and predicted switch target during NoC congestion analysis.
- ▌ Video Course To HTML Notes · caiyujie007 bundleUse when converting MP4/video lecture or screen-recorded slide courses into HTML study notes by extracting distinct PPT/slides, deduplicating annotation-only frames, generating per-slide screenshots plus Chinese "这是什么意思？" explanations, chapter index pages, and validation checks.
- ▌ Circuit Design Verification · caiyujie007General digital circuit and RTL design/verification workflow for any EDA toolchain. Use for RTL design discipline, reusable primitive/library selection, synthesis/lint sanity checks, simulation timeout policy, deadlock diagnosis, TB-vs-RTL responsibility decisions, waveform evidence review, and per-test waveform organization; tool-independent across Vivado, VCS, DC, Verdi, and similar tools.
- ▌ Hardware HTML Documentation · caiyujie007 bundleUse when creating or refactoring self-contained HTML documentation for RTL, digital circuits, microarchitecture, NoC/interconnect demos, or verification notes. The document should first explain the principle clearly, optionally with diagrams or animation, then describe circuit interfaces, map key principle-level ideas to RTL implementation, and finally summarize verification cases, waveform expectations, and artifacts.
- ▌ Paper Zh Annotated Translation · caiyujie007 bundleUse when translating an English technical or academic paper PDF into a Chinese paper-style annotated HTML, preserving the original paper layout and typography style as much as practical, translating the main content, and adding short principle explanations after key technical points.