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hdl-tools

@hdl-tools source repo

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• 17 skills
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• 13 hours ago last updated

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   Functional Verification · hdl-tools

   UVM-based functional verification — testbench architecture, test planning, directed and constrained-random stimulus, functional and code coverage closure, formal assist, and regression sign-off. Use when building a UVM testbench, writing tests, analysing coverage, or managing a verification regression.
   0 installs
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   Dft · hdl-tools

   Design for Test — scan architecture planning, scan insertion, ATPG pattern generation, MBIST for embedded memories, and JTAG boundary scan. Use when planning a DFT strategy, inserting scan, generating test patterns, or verifying that a chip will be testable in manufacturing.
   0 installs
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   Hls · hdl-tools

   High-Level Synthesis — C/C++ algorithm analysis, HLS directive optimisation, synthesis execution, and co-simulation verification. Use when converting C/C++ to synthesisable RTL, optimising for latency/throughput/area targets using pragmas, or verifying that generated RTL matches the golden C model.
   0 installs
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   Sta · hdl-tools

   Static timing analysis — multi-corner constraint validation, setup and hold analysis, timing exception review, and ECO guidance for closure. Use when running timing analysis on a design, reviewing timing violations, guiding ECO fixes, or performing timing sign-off for tape-out.
   0 installs
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   Physical Design · hdl-tools

   Full physical design flow — floorplan, placement, clock tree synthesis, routing, timing optimisation, power optimisation, area optimisation, and tape-out sign-off. Use when implementing a gate-level netlist through to GDS-II, closing timing and power, or performing any individual PD stage analysis.
   0 installs
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   Fpga Emulation · hdl-tools

   FPGA prototyping — ASIC-to-FPGA RTL adaptation, multi-FPGA partitioning, synthesis and timing closure on FPGA, hardware bring-up, and software validation on the prototype. Use when porting an ASIC design to Xilinx or Intel FPGA for pre-silicon software development and hardware validation.
   0 installs
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   Soc Integration · hdl-tools

   SoC IP integration — IP procurement and qualification, IP configuration, bus fabric setup, top-level RTL integration, and chip-level simulation. Use when assembling a SoC from multiple IP blocks, configuring an AXI bus interconnect, integrating memory macros, or running chip-level tests.
   0 installs
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   Rtl Design · hdl-tools

   SystemVerilog RTL design — module planning, coding standards enforcement, lint checking, CDC/RDC analysis, and synthesis readiness verification. Use when writing, reviewing, or debugging RTL for ASIC or FPGA targets, or when checking an existing RTL package for synthesis readiness.
   0 installs
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   Architecture · hdl-tools

   Microarchitecture exploration, PPA estimation, risk assessment, and architecture sign-off for digital chip design. Use when evaluating design candidates, estimating power/area/performance, assessing technical risk, or producing a microarchitecture document for handoff to RTL design.
   0 installs
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    Logic Synthesis · hdl-tools

    Logic synthesis from RTL to gate-level netlist — SDC constraint validation, compile and optimisation strategy, netlist quality check, and LEC equivalence verification. Use when synthesising RTL for ASIC, setting up timing constraints, optimising for timing/area/power, or verifying a post-synthesis netlist.
    0 installs
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    Embedded Firmware · hdl-tools

    Embedded firmware and device drivers — BSP development, peripheral driver implementation (UART, SPI, I2C, GPIO, DMA, Timer), RTOS integration (FreeRTOS, Zephyr), and system validation. Use when writing chip bring-up firmware, implementing HAL drivers, porting an RTOS, or validating firmware on hardware.
    0 installs
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    Formal Verification · hdl-tools

    Formal property verification (FPV) and logical equivalence checking (LEC). Use when proving design properties exhaustively, checking RTL vs gate-level netlist equivalence, verifying CDC crossings formally, or closing verification coverage gaps that simulation cannot efficiently reach.
    0 installs
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    Memory Ip Design · hdl-tools

    Embedded memory IP design — SRAM/register-file/ROM requirements capture, memory compiler and macro selection, array architecture (banking, ports, ECC wrapper), redundancy and repair allocation, view generation and QA, and integration handoff to DFT, PD, and STA. Use when specifying or selecting memory macros, architecting a memory subsystem, sizing spare rows/columns for repair, or qualifying a memory view set for a chip.
    0 installs
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    Compiler Toolchain · hdl-tools

    Compiler toolchain development for custom processor ISAs — LLVM/GCC backend, assembler, linker scripts, runtime libraries, and regression validation. Use when building a compiler for a custom RISC-V extension, proprietary ISA, or any processor where no existing toolchain targets it correctly.
    0 installs
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    Pipeline Orchestration · hdl-tools bundle

    Cross-domain loop orchestration for the chip design pipeline. Provides the fix_request protocol, iteration-cap logic, escalation templates, and dispatch patterns for routing verification/formal failures to the RTL orchestrator and back. Use when driving the closed-loop verification↔RTL feedback cycle.
    0 installs
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    Memory Keeper · hdl-tools bundle

    Distil accumulated experience records (experiences.jsonl) into updated domain knowledge summaries (knowledge.md) for any chip-design domain. Run after every 10 orchestrator sessions, or on demand when a domain has collected new issue/fix patterns.
    0 installs
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    Infrastructure · hdl-tools

    EDA tool detection, wrapper deployment, and MCP configuration for digital chip design environments. Use when setting up a new workstation, verifying tool availability before a domain flow, or generating per-tool install scripts with TCL modulefiles.
    0 installs