phamcuong21478
- 10 skills
- 0 followers
- 14 hours ago last updated
- ▌ Vdoc · phamcuong21478Aggregate all per-module documentation into a single comprehensive IP document
- ▌ Varch · phamcuong21478Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton
- ▌ Vfill · phamcuong21478Implement Verilog code from an approved design proposal, then lint and simulate
- ▌ Vflow · phamcuong21478 bundleScan project state to determine phase completion, write flow_status.md, and orchestrate the full RTL design flow from architecture to documentation
- ▌ Vdebug · phamcuong21478Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed
- ▌ Vsynth · phamcuong21478Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power
- ▌ Vdesign · phamcuong21478Generate a design proposal, documentation, and RTL backbone from a requirement file
- ▌
- ▌ Vtestgen · phamcuong21478 bundleScaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list
- ▌ Vtestrun · phamcuong21478Run all IP-level testcases from tc_list.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions