Shinei-Nouzen-Arch
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- ▌ Vitis Hls Synthesis · shinei-nouzen-arch bundleVitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.
- ▌ Vivado Constraints · shinei-nouzen-arch bundleUse this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (create_clock, create_generated_clock, virtual clocks), I/O delay constraints (set_input_delay, set_output_delay, DDR timing), timing exceptions (set_false_path, set_multicycle_path, set_max_delay, set_min_delay), clock domain crossing (CDC) constraints (set_clock_groups, set_bus_skew), clock uncertainty/jitter/latency, physical constraints (IOSTANDARD, PACKAGE_PIN, LOC, Pblock, placement, routing), XDC precedence rules, constraint scoping (SCOPED_TO_REF), constraint ordering optimization, or constraint debugging (check_timing, report_exceptions, report_clock_interaction). Trigger when the user mentions XDC, SDC, timing constraints, clock constraints, IO delay, false path, multicycle path, clock groups, or physical pin assignment. For timing report interpretation and analysis use vivado-analysis.
- ▌ Vivado Analysis · shinei-nouzen-arch bundleUse this skill when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis. Covers report_timing/report_timing_summary, slack and path analysis, clock skew/uncertainty, report_qor_assessment/suggestions, report_design_analysis for congestion and complexity, report_methodology, utilization, CDC/DRC/bus skew reports, message severity, waivers, and setup/hold closure strategy. This skill interprets reports and recommends next analysis steps. For TCL execution use vivado-tcl, for constraint changes use vivado-constraints, for implementation directives use vivado-impl, for full timing closure workflows use vivado-timing-closure.
- ▌ Vivado Debug · shinei-nouzen-arch bundleUse this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation, mark_debug attribute and debug probing flows (Netlist Insertion, HDL Instantiation), Set Up Debug Wizard, ILA cross-trigger architecture, debug core timing impact and mitigation, Vivado Hardware Manager operation, FPGA/SoC device programming, Versal debugging architecture (AXI4 Debug Hub, CIPS integration), SVF file programming, debug clock requirements, and common debug error troubleshooting. This skill provides debugging strategy and decision-making knowledge — for TCL command execution use vivado-tcl, for implementation strategies use vivado-impl, for timing analysis use vivado-analysis.
- ▌ Vivado Synth · shinei-nouzen-arch bundleUse this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCK_SYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control, FSM encoding, retiming, or asks how to optimize synthesis results for area/timing/power. This skill provides decision-making knowledge — for TCL command execution, use vivado-tcl skill.
- ▌ Vivado Impl · shinei-nouzen-arch bundleUse this skill when the user needs Vivado implementation strategy selection or optimization. Covers opt_design, power_opt_design, place_design, phys_opt_design, route_design, implementation directives/options, congestion-driven placement, fanout/placement/routing/SLR/register physical optimization, hold fixing, incremental implementation, ECO flow, and implementation run strategies for performance, congestion, area, and power. This skill chooses implementation-phase tactics and tradeoffs. For TCL command generation/execution use vivado-tcl, for synthesis use vivado-synth, for constraints use vivado-constraints, for report interpretation use vivado-analysis, for end-to-end timing closure use vivado-timing-closure.
- ▌ Vivado Sim · shinei-nouzen-arch bundleUse this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing simulation (SDF back-annotation, timing verification), Vivado Simulator xsim usage (xvlog/xvhdl/xelab/xsim three-step flow, launch_simulation Project Mode), third-party simulator integration (Questa/ModelSim/VCS/Xcelium/Riviera/ActiveHDL, compile_simlib, export_simulation), SAIF/VCD power simulation (open_saif/log_saif, open_vcd/log_vcd, read_saif + report_power), simulation netlist generation (write_verilog -mode funcsim/timesim, write_sdf), xsim debugging commands (add_force, add_wave, log_wave, add_bp, step, run, restart, get_objects, get_value), simulation properties and settings, glbl.v usage, or any question about choosing the right simulation approach for verification or power analysis.
- ▌ Vivado Tcl · shinei-nouzen-arch bundleGenerate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Covers project and non-project flows, synthesis, implementation, simulation, constraints, IP integration, and hardware programming. Use for explicit TCL requests or when scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again. For pure report interpretation, strategy selection, constraint theory, or debug planning, use the relevant analysis, synthesis, implementation, constraints, or debug skill as the primary guide. Combine those skills with this one when execution and verification are needed.
- ▌ Run Agentic Dse · shinei-nouzen-arch bundleInitialize, run, resume, and inspect FPGA HLS design-space exploration with Explorer, Exploiter, and Innovator workers. Also use for read-only requirement review, architecture advice, Pareto analysis, and convergence diagnosis without automatically launching experiments.