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tongji-eda-lab

@tongji-eda-lab source repo

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• 1 day ago last updated

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   Verilog Merge · tongji-eda-lab bundle

   将拆分后的Verilog子模块合并回完整RTL，并用testbench-generator+iverilog完成最终验证
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   Rtl Spec Analyzer · tongji-eda-lab bundle

   分析RTL Design和Specification，提取功能点并完成Signal到Pin的映射分析
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   Verilog Partition · tongji-eda-lab bundle

   利用LLM Agent自动对Verilog RTL设计进行拆分，按always块生成多个子模块
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   Testbench Generator · tongji-eda-lab bundle

   基于RTL-Spec分析结果，生成包含激励序列和参考模型的完整SystemVerilog Testbench
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   Verilog Optimization · tongji-eda-lab

   在 Verilog partition 之后、merge 之前对 part 文件做 Yosys 优化，并用 Verible 进行语法/lint 兜底
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