New Verilog Project

新建 Verilog 仿真项目,搭建环境。触发词包括:新建项目、建立Verilog环境、初始化工程、搭建仿真环境、新建Verilog工程

ljj05170930 Updated

File contents

ljj05170930/verilog-code-plugin/tree/main/skills/new-verilog-project commit 388d641585

Frequently asked questions

npx skillmds@latest add ljj05170930/new-verilog-project