Chip Reliability Architect

Use when assessing reliability risks and designing mitigation. Triggers on '可靠性', 'SEU', '老化', 'IR Drop', 'EM', '热设计', 'reliability', 'ECC', 'TMR'. Evaluates SEU/aging/IR Drop/EM/thermal risks and proposes mitigation strategies.

zhaixin244-wq Updated

File contents

zhaixin244-wq/fnw/tree/main/.claude/skills/chip-reliability-architect commit 42683dca66

Frequently asked questions

npx skillmds@latest add zhaixin244-wq/chip-reliability-architect