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1. ▌
   RAG Sync · zhaixin244-wq

   End-of-session review and sync of learnings to the personal LightRAG knowledge graph
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   RAG Remember · zhaixin244-wq

   Store a fact, decision, or observation into the personal LightRAG knowledge graph immediately
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   Claude Code Plugin Release · zhaixin244-wq bundle

   Automated semantic versioning and release workflow for Claude Code plugins. Handles version increments across package.json, marketplace.json, and plugin.json, build verification, git tagging, GitHub releases, and changelog generation.
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   RAG Project Sync · zhaixin244-wq

   End-of-session review and sync of project-specific learnings to the project-level LightRAG graph
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   RAG Project Query · zhaixin244-wq

   Query the project-level LightRAG knowledge graph for project-specific context and decisions
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   RAG Setup Project · zhaixin244-wq

   Set up LightRAG persistent memory for a Cursor project with MCP configuration
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   RAG Project Remember · zhaixin244-wq

   Store project-specific knowledge into the project-level LightRAG knowledge graph
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   Defuddle · zhaixin244-wq

   Strip clutter from web pages before ingesting into the wiki. Removes ads, navigation, headers, footers, and boilerplate: leaving clean readable markdown that saves 40-60% tokens. Triggers on: defuddle, clean this page, strip this url, fetch and clean, clean web content before ingesting, strip ads, remove clutter, clean URL content, readable markdown from URL.
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   Obsidian Bases · zhaixin244-wq

   Create and edit Obsidian Bases (.base files): Obsidian's native database layer for dynamic tables, card views, list views, filters, formulas, and summaries over vault notes. Triggers on: create a base, add a base file, obsidian bases, base view, filter notes, formula, database view, dynamic table, task tracker base, reading list base.
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    Obsidian Markdown · zhaixin244-wq

    Write correct Obsidian Flavored Markdown: wikilinks, embeds, callouts, properties, tags, highlights, math, and canvas syntax. Reference this when creating or editing any wiki page. Triggers on: write obsidian note, obsidian syntax, wikilink, callout, embed, obsidian markdown, wikilink format, callout syntax, embed syntax, obsidian formatting, how to write obsidian markdown.
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    Save · zhaixin244-wq

    Save the current conversation, answer, or insight into the Obsidian wiki vault as a structured note. Analyzes the chat, determines the right note type, creates frontmatter, files it in the correct wiki folder, and updates index, log, and hot cache. Triggers on: "save this", "save that answer", "/save", "file this", "save to wiki", "save this session", "file this conversation", "keep this", "save this analysis", "add this to the wiki".
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    Wiki · zhaixin244-wq bundle

    Claude + Obsidian knowledge companion. Sets up a persistent wiki vault, scaffolds structure from a one-sentence description, and routes to specialized sub-skills. Use for setup, scaffolding, cross-project referencing, and hot cache management. Triggers on: "set up wiki", "scaffold vault", "create knowledge base", "/wiki", "wiki setup", "obsidian vault", "knowledge base", "second brain setup", "running notetaker", "persistent memory", "llm wiki".
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    Canvas · zhaixin244-wq bundle

    Visual layer of the wiki. Add images, text cards, PDFs, and wiki pages to Obsidian canvas files with auto-positioning inside zones. Integrates with /banana for image capture. Triggers on: /canvas, canvas new, canvas add image, canvas add text, canvas add pdf, canvas add note, canvas zone, canvas list, canvas from banana, add to canvas, put this on the canvas, open canvas, create canvas.
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14. ▌
    Debate · zhaixin244-wq bundle

    Use when performing cross-model adversarial review of plans, architectures, or code. Triggers on 'debate', '辩论', '跨模型', '对手评审', 'adversarial review', '外部模型', 'cross-model'. Calls external LLM (Codex/Gemini/Kimi/GLM/MiMo/Claude) to challenge your plan with up to 3 rounds of adversarial iteration.
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    RAG Query · zhaixin244-wq

    Query the LLM Wiki knowledge base for protocol/CBB/architecture information
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    Wiki Fold · zhaixin244-wq bundle

    Rollup of wiki log entries into meta-pages. Reads the last 2^k entries from wiki/log.md, writes a structurally-idempotent fold page to wiki/folds/ that links back to children. Extractive summarization (no invention). Dry-run by default, stdout-only; commit mode writes and accepts that the PostToolUse hook auto-commits. Triggers on: fold the log, run a fold, run wiki-fold, log rollup, roll up log entries.
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    Wiki Lint · zhaixin244-wq

    Health check the Obsidian wiki vault. Finds orphan pages, dead wikilinks, stale claims, missing cross-references, frontmatter gaps, and empty sections. Creates or updates Dataview dashboards. Generates canvas maps. Triggers on: "lint", "health check", "clean up wiki", "check the wiki", "wiki maintenance", "find orphans", "wiki audit".
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18. ▌
    Mem Search · zhaixin244-wq

    Search claude-mem's persistent cross-session memory database. Use when user asks "did we already solve this?", "how did we do X last time?", or needs work from previous sessions.
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    Wiki Query · zhaixin244-wq

    Answer questions using the Obsidian wiki vault. Reads hot cache first, then index, then relevant pages. Synthesizes answers with citations. Files good answers back as wiki pages. Supports quick, standard, and deep modes. Triggers on: what do you know about, query:, what is, explain, summarize, find in wiki, search the wiki, based on the wiki, wiki query quick, wiki query deep.
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    Vf Pipeline · zhaixin244-wq bundle

    Use this skill to start or resume the VeriFlow RTL hardware design pipeline (architect to synth). Trigger this when the user asks to "run the RTL flow", "design hardware", or "start the pipeline". Pass the project directory path as the argument.
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    Wiki Ingest · zhaixin244-wq

    Ingest sources into the Obsidian wiki vault. Reads a source, extracts entities and concepts, creates or updates wiki pages, cross-references, and logs the operation. Supports files, URLs, and batch mode. Triggers on: ingest, process this source, add this to the wiki, read and file this, batch ingest, ingest all of these, ingest this url.
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    Autoresearch · zhaixin244-wq bundle

    Autonomous iterative research loop. Takes a topic, runs web searches, fetches sources, synthesizes findings, and files everything into the wiki as structured pages. Based on Karpathy's autoresearch pattern: program.md configures objectives and constraints, the loop runs until depth is reached, output goes directly into the knowledge base. Triggers on: "/autoresearch", "autoresearch", "research [topic]", "deep dive into [topic]", "investigate [topic]", "find everything about [topic]", "research and file", "go research", "build a wiki on".
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23. ▌
    Chip Create Dir · zhaixin244-wq bundle

    Use when initializing chip module workspace directory structure. Triggers on '创建目录', '初始化目录', '目录结构', 'workspace', '工作目录', 'create dir'. Creates ds (design) and dv (verification) directory trees with standard subdirectories.
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    Chip Doc Scorer · zhaixin244-wq

    芯片架构文档多维度评分器。对 FS 功能规格书、UA 微架构文档、RTL 代码进行 10 维度量化评分（总分100），集成跨文档一致性检查、风险加权评分、自动改进建议生成和评分→改进→复评闭环。支持单文档评分、批量评分、版本对比、闭环改进。触发词：'文档评分','文档打分','FS评分','UA评分','RTL评分','代码评分','架构评分','质量评分','doc score','文档质量检查','评分报告','评分改进','文档质量闭环'.
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25. ▌
    Chip Png D2 Gen · zhaixin244-wq bundle

    Use when generating D2 architecture diagrams, data flow diagrams, or FSM state machine diagrams. Triggers on 'd2', '架构图', '框图', '状态机图', 'diagram', '数据通路图', 'generate d2', '模块连接图'. Compiles .d2 source to PNG using dagre layout.
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    Deeptutor Setup · zhaixin244-wq

    DeepTutor 部署检测与安装配置。触发词：'部署 DeepTutor'、'安装 DeepTutor'、'检查 DeepTutor'、'配置 DeepTutor'、'deeptutor setup'。检测 CLI 可用性、Python venv、依赖完整性、.env 配置，缺失时自动部署。
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    Devils Advocate · zhaixin244-wq

    Use when challenging decisions, plans, architecture, or code by arguing the opposing side. Triggers on 'devil', '对抗', '挑战', 'poke holes', 'what could go wrong', 'linus', 'ruthless', '暴露风险', '假设盲点', 'stress test'. Supports 4 intensity levels: gentle, balanced, ruthless, linus.
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    Chip Cbb Decision · zhaixin244-wq

    Use when deciding whether to abstract RTL logic as a reusable CBB module. Triggers on 'CBB', '复用', '抽象', '可复用模块', 'CBB决策', 'reuse', 'abstraction'. Evaluates interface standardization, parameterization, self-containment and reuse value.
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    Chip Impl Sdc Sva · zhaixin244-wq

    Use when generating SDC constraints, SVA assertions or testbench for RTL. Triggers on 'SDC', 'SVA', 'testbench', '时钟约束', '断言', 'TB', '约束文件', 'assertion'. Generates clock constraints, SVA assertions and testbench based on microarch timing strategy.
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    Chip Lint Checker · zhaixin244-wq bundle

    Use when running RTL lint checks. Triggers on 'lint', 'verilator', 'verible', 'spyglass', '语法检查', '可综合性', '组合环路', 'latch检查', 'rtl lint', 'lint检查'. Supports multiple EDA tools with auto-detection.
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    Chip Cdc Architect · zhaixin244-wq

    Use when designing clock domain crossing architecture. Triggers on 'CDC', '跨时钟域', '时钟域', '同步策略', '多时钟', 'clock domain', '亚稳态', '双触发器'. Performs multi-clock domain partitioning, CDC signal identification and synchronization strategy design.
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    Chip Impl Delivery · zhaixin244-wq

    Use when verifying RTL implementation deliverables completeness before delivery. Triggers on '交付', 'delivery', '交付物', '交付清单', '完整性检查', 'deliverables'. Validates all deliverables exist and pass quality gates, outputs delivery checklist.
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    Chip Lint Resolver · zhaixin244-wq bundle

    Use when processing vc-spyglass lint log output to resolve violations. Maps lint rules to JMTAG execution levels, proposes RTL fixes or generates waive files. Triggered by keywords like spyglass, lint log, lint violation, JMTAG, waive file, lint rules.
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    Chip Ppa Formatter · zhaixin244-wq

    Use when formatting PPA specification tables. Triggers on 'PPA表', 'PPA格式', 'ppa formatter', '面积表', '功耗表', '性能表', 'PPA规格'. Outputs structured PPA specs with unit normalization and constraint expressions.
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    Chip Sdc Generator · zhaixin244-wq

    Use when generating comprehensive SDC timing constraints from FS/microarch documents. Triggers on '生成SDC', 'SDC约束', 'timing constraints', '时序约束文件', 'write SDC', 'SDC文件'. Produces production-quality SDC covering clocks, I/O, design rules, timing exceptions, and area/power constraints.
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    Deeptutor Research · zhaixin244-wq

    通过 DeepTutor CLI 进行体系化知识研究。触发词：'DeepTutor 研究'、'深度研究'、'知识库检索'、'RAG 检索'、'deeptutor search'、'deeptutor research'。封装 kb create/add、deep_research、kb search、deep_solve、chat 等 CLI 调用，输出结构化 JSON。
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    Chip Doc Structurer · zhaixin244-wq

    Use when designing microarchitecture document structure. Triggers on '文档结构', '章节设计', 'doc structure', '文档模板', '内容权重', '文档组织'. Designs chapter structure and content weight allocation for microarchitecture specifications.
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    Chip Impl Rtl Coding · zhaixin244-wq

    Use when implementing RTL code for chip submodules. Triggers on 'RTL实现', 'rtl coding', '写rtl', '代码实现', '数据通路', '控制逻辑', 'rtl code'. Implements data path, control logic, CBB integration and interface per submodule, strictly following architecture freeze.
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    Chip Impl Self Check · zhaixin244-wq

    Use when performing final self-check on RTL implementation before delivery. Triggers on '自检', 'self-check', 'self check', '实现自检', 'quality checklist', 'IC-01', 'IM-01', '检查清单'. Runs IC-01~39 + IM-01~08 implementation quality checklist.
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    Chip Rtl Bug Checker · zhaixin244-wq

    Use when checking RTL code for common bugs and design issues. Triggers on 'bug', 'rtl bug', '检查rtl', 'rtl检查', 'bug check', 'rtl review', '代码检查', '设计缺陷'. Runs 6-category analysis: pipeline/FSM, input latch, interface, FIFO/flow, bitwidth, resource conflict.
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41. ▌
    Claude Skill Verilog · zhaixin244-wq

    Verilog/SystemVerilog coding style and Verilator workflow guidance
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    Chip Arbiter Selector · zhaixin244-wq

    Use when selecting arbitration strategy for RTL modules. Triggers on '仲裁', 'arbiter', 'round-robin', 'RR', 'WRR', '优先级', '公平性', '饥饿', 'arbiter selector'. Based on request pattern, channel count and QoS, selects Fixed Priority / Round-Robin / WRR and evaluates starvation risk.
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    Chip Budget Allocator · zhaixin244-wq

    Use when allocating PPA budgets top-down to submodules. Triggers on 'PPA', '预算', 'budget', '面积分配', '功耗分配', '性能分配', 'PPA拆解', '预算闭合'. Decomposes system-level PPA targets to submodule budgets and verifies closure.
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    Chip Png Wavedrom Gen · zhaixin244-wq bundle

    Use when generating Wavedrom timing diagrams as PNG images. Triggers on '时序图', 'wavedrom', 'timing diagram', '波形图', '时序分析图', 'generate wavedrom'. Compiles Wavedrom JSON to PNG using wavedrom-cli.
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    Chip Spyglass Cdc Chk · zhaixin244-wq bundle

    Use when running SpyGlass CDC checks on RTL. Triggers on 'cdc检查', 'cdc check', 'spyglass cdc', '跨时钟域检查', 'cdc验证', 'clock domain crossing', 'cdc setup', 'cdc_verify'. Generates SGDC constraints, runs CDC goals, produces violation reports.
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    Chip Spyglass Rdc Chk · zhaixin244-wq bundle

    Use when running SpyGlass RDC checks on RTL. Triggers on 'rdc检查', 'rdc check', 'spyglass rdc', '复位域交叉检查', 'rdc验证', 'reset domain crossing', 'rdc setup', 'rdc_verify'. Generates RDC constraints, runs RDC goals, produces violation reports.
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47. ▌
    Chip Synthesis Runner · zhaixin244-wq

    Use when running Yosys synthesis on Verilog/RTL code. Triggers on '综合', 'synthesis', 'yosys', 'synth', '面积', 'timing', 'Fmax', '综合报告', '面积估计'. Runs Yosys and generates synthesis report with area and critical path info.
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    Chip Diagram Generator · zhaixin244-wq

    Use when generating chip module diagrams (block diagrams, timing diagrams, FSM diagrams). Triggers on '框图', '时序图', '状态机图', 'diagram', '架构图', '画图', '画一个'. Generates module block diagrams, timing diagrams and state machine diagrams. Primary format: D2→PNG for block/FSM diagrams, Wavedrom→PNG for timing diagrams.
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    Chip Impl Input Triage · zhaixin244-wq

    Use when checking RTL implementation input completeness before coding. Triggers on '输入确认', 'input triage', '输入检查', '文档完整性', '输入分类', 'input check'. Checks microarch docs, coding style, CBB list completeness and selects execution path.
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    Chip Impl Parallel Dev · zhaixin244-wq

    Use when running parallel RTL development across multiple submodules. Triggers on '并行开发', 'parallel', '多模块并行', '并行subagent', 'parallel dev', '并行调度'. Coordinates Plan Mode analysis, parallel subagent dispatch, top-level integration and PR confirmation.
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51. ▌
    Chip Impl Quality Gate · zhaixin244-wq

    Use when running lint checks, synthesis, or quality gates on RTL code. Triggers on '综合', 'lint', 'synth', 'quality gate', '质量门禁', '门禁', 'verilator', 'yosys', '自检', 'check'. Executes lint+synth checks with auto-heal loop on failures.
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    Chip Png Interface Gen · zhaixin244-wq bundle

    Use when generating interface port PNG diagrams from Verilog module declarations. Triggers on '接口图', '端口图', 'interface gen', 'port diagram', '接口PNG', 'module snapshot'. Generates module_snapshot style port PNGs with inputs on left, outputs on right, signal names with width and direction arrows.
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    Chip Review Checklister · zhaixin244-wq

    Use when reviewing FS, UA, or RTL documents against quality checklists. Triggers on 'review', '评审', '检查清单', 'checklist', 'review report', '评审报告', '自检报告'. Generates structured review checklist and report.
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    Chip Low Power Architect · zhaixin244-wq

    Use when designing low-power architecture for chip modules. Triggers on '低功耗', 'UPF', '功耗域', 'power domain', 'isolation', 'retention', 'clock gating', 'power gating'. Designs power domain partitioning, isolation/retention strategy and UPF.
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    Chip Traceability Linker · zhaixin244-wq

    Use when building requirements traceability matrix (RTM). Triggers on 'RTM', '追溯矩阵', 'traceability', '需求追溯', '需求覆盖', '追溯矩阵'. Builds traceability from requirements to architecture, interface, PPA and verification.
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    Chip Interface Contractor · zhaixin244-wq

    Use when defining module interface contracts. Triggers on '接口契约', 'interface contract', '信号列表', '接口定义', '端口定义', '接口时序'. Defines signal list, timing, protocol behavior and SVA for module interfaces.
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    Chip Cbb Exception Confirm · zhaixin244-wq

    Use when standard CBB cannot fully meet requirements and user confirmation is needed. Triggers on 'CBB例外', 'CBB差异', '复用还是自研', 'CBB exception', 'CBB confirm'. Lists differences item by item and confirms reuse vs custom development with user.
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    Chip Design Space Explorer · zhaixin244-wq

    Use when exploring PPA design space for optimal solutions. Triggers on '设计空间', 'DSE', '帕累托', 'pareto', 'PPA探索', '方案比选', 'trade-off', 'design space'. Performs Area-Performance-Power 3D exploration to find Pareto-optimal set.
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    Chip Impl Module Structure · zhaixin244-wq

    Use when planning RTL module structure from microarchitecture docs. Triggers on '模块结构', '端口列表', '子模块划分', '文件清单', 'module structure', 'port list'. Extracts ports, submodule partitioning and file list from microarch docs.
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    Chip Reliability Architect · zhaixin244-wq

    Use when assessing reliability risks and designing mitigation. Triggers on '可靠性', 'SEU', '老化', 'IR Drop', 'EM', '热设计', 'reliability', 'ECC', 'TMR'. Evaluates SEU/aging/IR Drop/EM/thermal risks and proposes mitigation strategies.
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    Chip Spyglass Cdc Resolver · zhaixin244-wq bundle

    Use when processing SpyGlass CDC reports to resolve violations. Triggers on 'cdc违例', 'cdc violation', 'cdc report', 'cdc分析', 'cdc waive', 'cdc修复', 'cdc resolver'. Maps CDC rules to priority levels, proposes RTL fixes or generates waiver files.
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    Chip Spyglass Rdc Resolver · zhaixin244-wq bundle

    Use when processing SpyGlass RDC reports to resolve violations. Triggers on 'rdc违例', 'rdc violation', 'rdc report', 'rdc分析', 'rdc waive', 'rdc修复', 'rdc resolver'. Maps RDC rules to priority levels, proposes RTL fixes or generates waiver files.
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    Chip Version Diff Generator · zhaixin244-wq

    Use when comparing architecture document versions and generating change impact analysis. Triggers on '版本对比', 'version diff', '变更分析', '变更影响', '文档对比', 'change impact'. Compares two versions of architecture docs and outputs structured change impact analysis.
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    Chip Rtl Guideline Generator · zhaixin244-wq

    Use when generating RTL coding guidelines from microarchitecture. Triggers on '编码规范', 'coding guideline', 'RTL指导', '实现指导', '可综合性', 'rtl guideline', '编码指南', 'coding guide'. Generates RTL coding standards and synthesizability implementation guidance from microarch design.
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    Chip Microarch Chart Workflow · zhaixin244-wq

    Use when generating microarchitecture charts (D2, Wavedrom, Interface diagrams). Triggers on '图表生成', 'chart workflow', 'D2编译', 'wavedrom编译', '接口图', '图表工作流', 'generate charts'. Orchestrates D2/Wavedrom/Interface chart generation, compilation and validation.
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    Chip Protocol Compliance Checker · zhaixin244-wq

    Use when checking module interface protocol compliance. Triggers on '协议检查', 'protocol check', 'AXI合规', 'APB合规', '协议合规', '接口规范', 'compliance'. Checks module interfaces against AXI/CHI/TileLink/APB protocol specifications.
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