codejunkie99
- 120 skills
- 0 followers
- 8 hours ago last updated
- ▌ Gf Lint · codejunkie99SystemVerilog lint checker with structured output for orchestration. Runs Verilator lint, categorizes errors/warnings, explains issues, and returns a parseable result block for /gf orchestration.
- ▌ Gf Plan · codejunkie99 bundleHardware design planner - Creates comprehensive RTL implementation plans. This skill should be used when the user wants to plan a new design, architect a complex feature, or understand how to implement hardware before coding. Example requests: "plan a DMA controller", "design a UART", "architect the memory subsystem"
- ▌ Gf Build · codejunkie99Parallel build orchestrator for SystemVerilog creation tasks. Decomposes designs into independent modules, builds in parallel phases, runs verification on each component, then integrates. Example: "/gf-build RISC-V CPU with ALU, regfile, decoder, control FSM"
- ▌ Gf Learn · codejunkie99SystemVerilog learning mode — generates exercises, reviews solutions, and teaches RTL design patterns. Use when the user wants to learn SystemVerilog, practice hardware design, get exercises, or understand verification methodology.
- ▌ Gf Synth · codejunkie99Synthesize SystemVerilog/Verilog with Yosys. Reports area, timing, and resource utilization. Warns about unsupported SV constructs. Example: "synthesize my design for iCE40"
- ▌ Gf Cocotb · codejunkie99Python-based testbench generation using Cocotb. Alternative to SystemVerilog testbenches for Python-native hardware engineers. Example: "create a cocotb test for the FIFO", "write Python testbench"
- ▌ Gf Errors · codejunkie99Error translation layer for hardware tool outputs. Converts cryptic Verilator, Yosys, GHDL, and simulation errors into 3-layer explanations. Used internally by gf orchestrator — not user-invocable directly.
- ▌ Gf Expand · codejunkie99Expand mode - asks clarifying questions, presents options with trade-offs, then hands off to appropriate skill/agent with enriched context.
- ▌ Gf Formal · codejunkie99 bundleFormal verification from natural language. Generates SVA properties, configures SymbiYosys, runs proofs, and explains results. Example: "formally verify the FIFO never overflows"
- ▌ Gf Pinmap · codejunkie99Board-aware pin mapping. Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with correct pin assignments, I/O standards, and drive strength for target boards. Example: "map SPI to PMOD JA on Arty A7", "generate constraints for my iCEBreaker"
- ▌ Gf Router · codejunkie99 bundleFigures out what kind of digital hardware design task the user wants to do, then hands off to the right specialist. Use when the request is unclear, multi-step, or needs help deciding whether to simulate, synthesize, lint, or implement.
- ▌ Gf Fusesoc · codejunkie99FuseSoC build system integration for GateFlow. Generates .core files and drives synthesis/simulation through Edalize backends (Vivado, Quartus, open-source tools). Use when the user needs to create a FuseSoC core file, build with Edalize, or integrate RTL into a FuseSoC project.
- ▌ Gf Project · codejunkie99Manages .gateflow/project.yaml for project-specific configuration. Auto-detects project settings or prompts user for board, HDL, and target. Used internally by other skills — not typically invoked directly.
- ▌ Gf Release · codejunkie99GateFlow release readiness workflow. Validates plugin manifests, marketplace metadata, docs index coverage, root mirrors, release notes, and component counts before a version tag is created. Use when preparing, checking, or cutting a GateFlow plugin release.
- ▌ Gf Summary · codejunkie99Summarize Verilator, lint, or simulation output into a readable, actionable format. Use when the user wants to understand build output, lint errors, or simulation results from a Verilator or EDA tool run.
- ▌ Gf Architect · codejunkie99Codebase architect - Maps and documents SystemVerilog projects. This skill should be used when the user wants to understand a codebase structure, generate architecture documentation, or onboard to a new RTL project. Example requests: "map this codebase", "document the architecture", "show module hierarchy"
- ▌ Gf Ip Detect · codejunkie99Auto-detect IP blocks within FPGA and hardware codebases. Scans for module instantiations, identifies missing implementations, matches standard IP patterns, and dispatches agents to fill gaps. Example: "scan for missing IP blocks", "detect what needs implementing", "find unimplemented modules", "auto-fill IP blocks"
- ▌ Gf Learn Ctx · codejunkie99Contextual learning — micro-lessons embedded in workflow output. Explains hardware concepts on first encounter, tracks what has been taught, generates practice exercises on demand. Used internally by orchestrator — not typically invoked directly.
- ▌ Gf Protocols · codejunkie99 bundleProtocol scaffolding library. Generates correct, readable protocol interface scaffolds (AXI4-Lite, SPI, UART, I2C, AXI4-Full, AXI-Stream, Wishbone) with testbench templates and integration examples. Example: "create an I2C master interface", "scaffold AXI-Stream source"
- ▌ Tb Best Practices · codejunkie99Testbench verification best practices and patterns. This skill should be used when the user needs testbench architecture guidance, verification methodology, or wants to write professional-quality testbenches. Example requests: "testbench best practices", "how to structure TB", "verification patterns"