deanyou
- 40 skills
- 0 followers
- 4 hours ago last updated
- ▌ Maestro 2 · deanyouMaestro (ADE Assembler) session management and simulation. Use when: running simulations via Maestro, configuring tests/analyses/outputs, updating design variables, reading results.
- ▌ Sim Run 2 · deanyouRun circuit simulation (DC, tran, AC) on Virtuoso. Use when executing Spectre simulation, running analysis, or checking simulation results.
- ▌ Sim Plot 2 · deanyou bundleVisualize Virtuoso simulation results as matplotlib charts. Use after: (1) sim sweep — line plot of measurements vs swept variable, (2) sim corner — grouped bar chart across PVT corners, (3) sim measure — horizontal bar of scalar measurements, (4) AC/Bode plot from PSF getData results (magnitude + phase), (5) process_data lookup tables — gm/Id curves for all L values. Auto-detects chart type from JSON structure. Saves PNG via plot_sim.py.
- ▌ Veriloga 2 · deanyou bundleDesign, write, and debug Verilog-A behavioral models for Cadence Virtuoso/Spectre simulation. Use when creating Verilog-A modules (voltage sources, behavioral models, testbench stimuli, ideal components), debugging Spectre simulation errors with Verilog-A, or when the user mentions veriloga, behavioral model, or ideal component.
- ▌ Sim Setup 2 · deanyouSet up Virtuoso simulation with Ocean SKILL. Use when configuring simulator, design target, model files, or design variables before running simulation.
- ▌ Skill Exec 2 · deanyouExecute SKILL code on Virtuoso. Use when running SKILL expressions, querying cellview data, listing libraries/cells, or interacting with Virtuoso programmatically.
- ▌ Cell Explore 2 · deanyouExplore Virtuoso cellviews - list libraries, cells, instances, nets, layers, and hierarchy. Use when browsing a design, understanding circuit topology, or inspecting layout/schematic contents.
- ▌ Schematic Gen 2 · deanyouGenerate Virtuoso schematics from topology descriptions via vcli schematic commands. Use when: (1) user wants to draw/create a schematic in Virtuoso, (2) user says "draw the OTA" or "create the schematic", (3) after sizing is complete and ready to build the circuit, (4) user provides a topology and wants it instantiated.
- ▌ Tunnel Connect 2 · deanyouConnect to Virtuoso via SSH tunnel or local bridge. Use when setting up Virtuoso connection, starting the bridge, or troubleshooting connectivity issues.
- ▌ Circuit Optimizer 2 · deanyou bundleBayesian optimization for circuit auto-tuning — closed-loop optimizer where Claude acts as the BO engine. Sweeps gm/Id + L parameters, runs Spectre, scores against specs, and iterates. Supports progressive PVT corners. Use when optimizing circuit sizing, auto-tuning amplifier parameters, or running design-space exploration. Triggers on "optimize", "auto-tune", "bayesian", "find best sizing".
- ▌ Ocean Netlist Regen 2 · deanyouFix Ocean SKILL simulation failures after schematic edits. Use when: (1) run() returns nil in <1s with no spectre.out, (2) createNetlist() returns nil, (3) sim results are all nil after changing W/L to design variables, (4) netlist file was deleted or is stale, (5) sim run previously worked but now fails after calling `sim setup` again, (6) OSSHNL-109 error after SKILL edit, (7) library not found / ddGetObj returns nil / Virtuoso started from wrong directory. Covers: the resultsDir binding trap (MOST COMMON), OSSHNL-109 extraction timestamp stale error, stale netlists, sim setup disrupting sessions, direct spectre invocation as bypass, library-not-registered diagnosis, and PSF signal naming.
- ▌ Skill Shell Gotchas 2 · deanyouCritical SKILL language gotchas when integrating with shell/IPC in Cadence Virtuoso. Use when: (1) ipcBeginProcess exits with state=127 (command not found), (2) sh() returns unexpected values like "t" instead of command output, (3) trying to capture shell stdout in SKILL, (4) writing files from SKILL with fprintf/outfile producing 0-byte output, (5) getpid() undefined error in SKILL.
- ▌ Spectre Netlist Gotchas 2 · deanyou bundleCritical Spectre netlist-mode gotchas for standalone simulation (no Virtuoso ADE). Use when: (1) writing Spectre testbench .scs files with `simulator lang=spectre`, (2) noise analysis shows absurd values (megavolts of noise) — oprobe topology is wrong, (3) SFE-30 error on `ac=1` in vsource — use `mag=1` in native Spectre lang, (4) SFE-1997 error on `oprobe=<node_name>` — must be a circuit element not a node, (5) parsing PSF ASCII output from Spectre (dc_op.dc, ac_gain.ac, noise_an.noise), (6) phase margin calculation for inverting amplifier topologies, (7) slew rate measurement gives wrong result with small-signal step — need large signal, (8) ICMR from DC sweep — use transistor region fields, not CM gain (which is ≈ 0), (9) SFE-868 from ADE-generated netlist — oa/lib/../ model path only works in ADE interactive mode.
- ▌ Diag · deanyouRead-only diagnostics for stuck Virtuoso state via `vcli diag ...`. Use when: (1) a cellview won't open and you suspect `.cdslck` lock conflicts, (2) "why is this view held by someone?" — find the holder without deleting anything, (3) a modal dialog has deadlocked the CIW and the SKILL path can't help (use `vcli window dismiss-dialog --x11` instead).
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- ▌ Sim Run · deanyouRun circuit simulation (DC, tran, AC) on Virtuoso. Use when executing Spectre simulation, running analysis, or checking simulation results.
- ▌ Sim Plot · deanyou bundleVisualize Virtuoso simulation results as matplotlib charts. Use after: (1) sim sweep — line plot of measurements vs swept variable, (2) sim corner — grouped bar chart across PVT corners, (3) sim measure — horizontal bar of scalar measurements, (4) AC/Bode plot from PSF getData results (magnitude + phase), (5) process_data lookup tables — gm/Id curves for all L values. Auto-detects chart type from JSON structure. Saves PNG via plot_sim.py.
- ▌ Veriloga · deanyouDesign, write, and debug Verilog-A behavioral models for Cadence Virtuoso/Spectre simulation. Use when creating Verilog-A modules (voltage sources, behavioral models, testbench stimuli, ideal components), debugging Spectre simulation errors with Verilog-A, or when the user mentions veriloga, behavioral model, or ideal component.
- ▌ Sim Setup · deanyouSet up Virtuoso simulation with Ocean SKILL. Use when configuring simulator, design target, model files, or design variables before running simulation.
- ▌ Sim Sweep · deanyouRun parameter sweeps and PVT corner simulations on Virtuoso. Use when sweeping design variables, running corner analysis, or characterizing circuits across operating conditions.
- ▌ Gm Over Id · deanyougm/Id methodology for analog IC design — transistor sizing via lookup table approach. Use when designing amplifiers, current mirrors, OTAs, or any analog circuit where you need to determine W/L from specs (GBW, gain, noise). Also use when the user mentions gm/id, transistor sizing, Vov, current density, or design space exploration.
- ▌ Skill Exec · deanyouExecute SKILL code on Virtuoso. Use when running SKILL expressions, querying cellview data, listing libraries/cells, or interacting with Virtuoso programmatically.
- ▌ Amp Copilot · deanyouAmplifier design copilot — topology selection, sizing via gm/Id lookup tables, PVT corner validation, and process-portable design. Use when designing amplifiers (OTA, opamp, comparator), selecting topology from specs, sizing transistors, or characterizing a new process node. Also triggers on keywords like amplifier, OTA, opamp, gain-bandwidth, CMRR, PSRR, slew rate.
- ▌ Sim Measure · deanyouExtract waveform measurements from Virtuoso simulation results. Use when measuring voltage, current, gm, gm/Id, bandwidth, settling time, or any simulation metric.
- ▌ Cell Explore · deanyouExplore Virtuoso cellviews - list libraries, cells, instances, nets, layers, and hierarchy. Use when browsing a design, understanding circuit topology, or inspecting layout/schematic contents.
- ▌ Skill Review · deanyouAudit a Claude Code skill file against the official skills specification. Use when the user asks to review, audit, or check a skill for spec compliance, or when a skill file may be too long, have wrong frontmatter, or needs structural improvement.
- ▌ Schematic Gen · deanyouGenerate Virtuoso schematics from topology descriptions via vcli schematic commands. Use when: (1) user wants to draw/create a schematic in Virtuoso, (2) user says "draw the OTA" or "create the schematic", (3) after sizing is complete and ready to build the circuit, (4) user provides a topology and wants it instantiated.
- ▌ Porting Skill · deanyouPort circuit simulation setups from one PDK or process technology to another. Use this skill whenever migrating Maestro/ADE sessions, Ocean setup scripts, or Spectre netlists to a different foundry or process node — for example SMIC 28nm to TSMC 40nm, a PDK version update within the same node, or an IC23.1 to IC25 tool upgrade. Triggers on: "migrate to new PDK", "switch process node", "corner names changed after PDK update", "model file paths broken", "port simulation to new technology", "move design to different foundry", "Lmin changed", "new supply voltage", "our .sdb corners don't match new PDK", or any mention of PDK/process transition. Invoke this skill proactively when you detect PDK-specific paths or corner names in netlists that don't match the target environment.
- ▌ Tunnel Connect · deanyouConnect to Virtuoso via SSH tunnel or local bridge. Use when setting up Virtuoso connection, starting the bridge, or troubleshooting connectivity issues.
- ▌ Digital Import · deanyouImport P&R (Genus + Innovus) products into Virtuoso: GDS layout, Verilog schematic/symbol, power labels, and label restyling. Four-step pipeline driven entirely from vcli skill exec — no Python bridge or GUI required. Use when: (1) user wants to pull a routed GDS or post-P&R netlist into Virtuoso, (2) layout labels look giant/unreadable after import, (3) user mentions strmin / ihdl / digital import / P&R-to-schematic flow.
- ▌ History Evolve · deanyouEvolve skills from vcli session history. Use when: (1) user says "根據歷史進化技能" / "evolve skills from history" / "覆盤技能", (2) after a debugging session to capture what went wrong, (3) periodic skill maintenance to close knowledge gaps revealed by real usage. Reads cmd.jsonl + per-session SKILL logs, finds failure/correction/gap signals, maps them to skills in .claude/skills/, and writes concrete improvements.
- ▌ Circuit Optimizer · deanyouBayesian optimization for circuit auto-tuning — closed-loop optimizer where Codex acts as the BO engine. Sweeps gm/Id + L parameters, runs Spectre, scores against specs, and iterates. Supports progressive PVT corners. Use when optimizing circuit sizing, auto-tuning amplifier parameters, or running design-space exploration. Triggers on "optimize", "auto-tune", "bayesian", "find best sizing".
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- ▌ Ocean Netlist Regen · deanyouFix Ocean SKILL simulation failures after schematic edits. Use when: (1) run() returns nil in <1s with no spectre.out, (2) createNetlist() returns nil, (3) sim results are all nil after changing W/L to design variables, (4) netlist file was deleted or is stale, (5) sim run previously worked but now fails after calling `sim setup` again. Covers: the resultsDir binding trap (MOST COMMON), stale netlists, sim setup disrupting sessions, direct spectre invocation as bypass, and PSF signal naming (I0.NM0 prefix).
- ▌ Skill Shell Gotchas · deanyouCritical SKILL language gotchas when integrating with shell/IPC in Cadence Virtuoso. Use when: (1) ipcBeginProcess exits with state=127 (command not found), (2) sh() returns unexpected values like "t" instead of command output, (3) trying to capture shell stdout in SKILL, (4) writing files from SKILL with fprintf/outfile producing 0-byte output, (5) getpid() undefined error in SKILL.
- ▌ Maestro Read Results · deanyou bundleRead Maestro/ADE simulation output values directly from PSF binary files — no Virtuoso GUI or bridge required. Parses maestro.sdb + active.state XML to extract output expressions, resolves the PSF directory from history.sdb, evaluates Ocean-style expressions (getData, dB20, phaseDeg, bandwidth, ymax, VF, VT…), and returns structured JSON results. Use this skill whenever: - The user asks "what is the gain / phase margin / bandwidth from the simulation?" - `maeGetOutputValue` returned nil (requires GUI results loaded in memory) - The user wants to check simulation results offline or from a script - The user wants to read PSF files / evaluate output expressions from a Maestro session - Any request involving Maestro output expressions, PSF files, or ADE results without GUI
- ▌ Pr Review Hardening · deanyou bundleVerify the accuracy of a GitHub PR review (or a pasted review draft) against the actual code before acting, fix the confirmed bugs one seam at a time, and confirm with the real CI run rather than trusting local-green. Use when the user hands over a PR review and asks to fix the review comments, apply these changes, review this and merge, or confirm whether a review is accurate. This skill applies when the task involves acting on a code review, a GitHub PR, the gh CLI, CI verification, or single-seam commit discipline.
- ▌ Spectre Netlist Gotchas · deanyouCritical Spectre netlist-mode gotchas for standalone simulation (no Virtuoso ADE). Use when: (1) writing Spectre testbench .scs files with `simulator lang=spectre`, (2) noise analysis shows absurd values (megavolts of noise) — oprobe topology is wrong, (3) SFE-30 error on `ac=1` in vsource — use `mag=1` in native Spectre lang, (4) SFE-1997 error on `oprobe=<node_name>` — must be a circuit element not a node, (5) parsing PSF ASCII output from Spectre (dc_op.dc, ac_gain.ac, noise_an.noise), (6) phase margin calculation for inverting amplifier topologies, (7) slew rate measurement gives wrong result with small-signal step — need large signal, (8) ICMR from DC sweep — use transistor region fields, not CM gain (which is ≈ 0).
- ▌ Spectre Netlist Template · deanyou bundleAdd stimulus and analysis templates to a Spectre netlist that has no excitation. Use when: (1) Ocean/ADE-generated netlist has no testbench wrapper (no vsource, no analysis statements), (2) you need to measure a specific figure of merit (GBW, PM, PSRR, CMRR, noise, load regulation, offset, propagation delay, etc.), (3) you are setting up standalone Spectre simulation from a bare subcircuit netlist. Identifies circuit type from port names / device types, then inserts the matching stimulus + analysis block from the canonical templates below.
- ▌ Spec Driven Circuit Design · deanyouSpec-driven analog circuit design — decompose system specs into block/transistor-level requirements, validate feasibility via simulation, and iterate. Use when defining amplifier specs, checking if specs are achievable, decomposing system requirements to circuit blocks, or when the user says "design spec", "spec review", "is this spec feasible", or "spec breakdown".